[llvm] [AMDGPU] Multi dword spilling for unaligned tuples (PR #183701)

[Juan Manuel Martinez Caamaño via llvm-commits]

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@@ -1561,14 +1565,24 @@ void SIRegisterInfo::buildSpillLoadStore(
   // Always use 4 byte operations for AGPRs because we need to scavenge
   // a temporary VGPR.
   // If we're using a block operation, the element should be the whole block.
-  // For misaligned registers, use 4-byte elements to avoid alignment errors.
+  // clang-format off
   unsigned EltSize = IsBlock ? RegWidth
-                     : (IsFlat && !IsAGPR && !IsRegMisaligned)
+                     : (IsFlat && !IsAGPR)
                          ? std::min(RegWidth, 16u)
                          : 4u;
+  // clang-format on
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jmmartinez wrote:

What do you think about splitting a bit this assignment instead of disabling clang-format. We could even inline the comment above and make the condition match the comments.

Why non-flat uses a `4u` `EltSize`? 

https://github.com/llvm/llvm-project/pull/183701