[llvm] [SPIR-V] Add support for arbitrary precision integer constants in instruction printer (PR #185306)
via llvm-commits
llvm-commits at lists.llvm.org
Sun Mar 8 11:05:21 PDT 2026
https://github.com/YixingZhang007 updated https://github.com/llvm/llvm-project/pull/185306
>From ec6c45dbc54d8d8c52b3675e76eb6c529a6200cc Mon Sep 17 00:00:00 2001
From: "yixing.zhang" <yixingzh at smtp.igk.intel.com>
Date: Fri, 6 Mar 2026 19:33:22 +0100
Subject: [PATCH 1/6] initial change for instruction printer
---
.../SPIRV/MCTargetDesc/SPIRVInstPrinter.cpp | 9 ++++++--
llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp | 19 +++++++++++-----
llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h | 2 +-
...SPV_ALTERA_arbitrary_precision_integers.ll | 22 +++++++++++++++++++
4 files changed, 43 insertions(+), 9 deletions(-)
diff --git a/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVInstPrinter.cpp b/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVInstPrinter.cpp
index 66500f5626fd1..498f0255ae4eb 100644
--- a/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVInstPrinter.cpp
+++ b/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVInstPrinter.cpp
@@ -53,8 +53,13 @@ void SPIRVInstPrinter::printOpConstantVarOps(const MCInst *MI,
if (MI->getOpcode() == SPIRV::OpConstantI && NumVarOps > 2) {
// SPV_ALTERA_arbitrary_precision_integers allows for integer widths greater
// than 64, which will be encoded via multiple operands.
- for (unsigned I = StartIndex; I != MI->getNumOperands(); ++I)
- O << ' ' << MI->getOperand(I).getImm();
+ const unsigned TotalBits = NumVarOps * 32;
+ APInt Val(TotalBits, 0);
+ for (unsigned i = 0; i < NumVarOps; ++i) {
+ uint64_t Word = MI->getOperand(StartIndex + i).getImm();
+ Val |= APInt(TotalBits, Word) << (i * 32);
+ }
+ O << Val;
return;
}
diff --git a/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp b/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
index 9a85634c82626..5ee0f71099f06 100644
--- a/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
@@ -153,6 +153,8 @@ SPIRVTypeInst SPIRVGlobalRegistry::getOpTypeBool(MachineIRBuilder &MIRBuilder) {
unsigned SPIRVGlobalRegistry::adjustOpTypeIntWidth(unsigned Width) const {
const SPIRVSubtarget &ST = cast<SPIRVSubtarget>(CurMF->getSubtarget());
+ if (Width > 1024)
+ report_fatal_error("Unsupported integer width!");
if (ST.canUseExtension(
SPIRV::Extension::SPV_ALTERA_arbitrary_precision_integers) ||
(Width == 4 && ST.canUseExtension(SPIRV::Extension::SPV_INTEL_int4)))
@@ -167,7 +169,7 @@ unsigned SPIRVGlobalRegistry::adjustOpTypeIntWidth(unsigned Width) const {
return 64;
else if (Width <= 128)
return 128;
- reportFatalUsageError("Unsupported Integer width!");
+ return Width;
}
SPIRVTypeInst SPIRVGlobalRegistry::getOpTypeInt(unsigned Width,
@@ -406,7 +408,7 @@ Register SPIRVGlobalRegistry::getOrCreateConstInt(const APInt &Val,
return createConstInt(CI, I, SpvType, TII, ZeroAsNull);
}
-Register SPIRVGlobalRegistry::createConstInt(const ConstantInt *CI,
+Register SPIRVGlobalRegistry::createConstInt(const Constant *CA,
MachineInstr &I,
SPIRVTypeInst SpvType,
const SPIRVInstrInfo &TII,
@@ -425,15 +427,20 @@ Register SPIRVGlobalRegistry::createConstInt(const ConstantInt *CI,
MachineInstrBuilder MIB;
if (BitWidth == 1) {
MIB = MIRBuilder
- .buildInstr(CI->isZero() ? SPIRV::OpConstantFalse
+ .buildInstr(CA->isNegativeZeroValue() ? SPIRV::OpConstantFalse
: SPIRV::OpConstantTrue)
.addDef(Res)
.addUse(getSPIRVTypeID(SpvType));
- } else if (!CI->isZero() || !ZeroAsNull) {
+ } else if (!CA->isNegativeZeroValue() || !ZeroAsNull) {
MIB = MIRBuilder.buildInstr(SPIRV::OpConstantI)
.addDef(Res)
.addUse(getSPIRVTypeID(SpvType));
- addNumImm(CI->getValue(), MIB);
+ if (BitWidth <= 64) {
+ const ConstantInt *CI = dyn_cast<ConstantInt>(CA);
+ addNumImm(APInt(BitWidth, CI->getZExtValue()), MIB);
+ } else {
+ addNumImm(CA->getUniqueInteger(), MIB);
+ }
} else {
MIB = MIRBuilder.buildInstr(SPIRV::OpConstantNull)
.addDef(Res)
@@ -445,7 +452,7 @@ Register SPIRVGlobalRegistry::createConstInt(const ConstantInt *CI,
*ST.getRegBankInfo());
return MIB;
});
- add(CI, Const);
+ add(CA, Const);
return Res;
}
diff --git a/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h b/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h
index 7296f2c0bf351..bd9bdfa759961 100644
--- a/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h
+++ b/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h
@@ -531,7 +531,7 @@ class SPIRVGlobalRegistry : public SPIRVIRMapping {
Register getOrCreateConstInt(const APInt &Val, MachineInstr &I,
SPIRVTypeInst SpvType, const SPIRVInstrInfo &TII,
bool ZeroAsNull = true);
- Register createConstInt(const ConstantInt *CI, MachineInstr &I,
+ Register createConstInt(const Constant *CA, MachineInstr &I,
SPIRVTypeInst SpvType, const SPIRVInstrInfo &TII,
bool ZeroAsNull);
Register getOrCreateConstFP(APFloat Val, MachineInstr &I,
diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_ALTERA_arbitrary_precision_integers/SPV_ALTERA_arbitrary_precision_integers.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_ALTERA_arbitrary_precision_integers/SPV_ALTERA_arbitrary_precision_integers.ll
index 9ea8a5709154c..a0451278f82cd 100644
--- a/llvm/test/CodeGen/SPIRV/extensions/SPV_ALTERA_arbitrary_precision_integers/SPV_ALTERA_arbitrary_precision_integers.ll
+++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_ALTERA_arbitrary_precision_integers/SPV_ALTERA_arbitrary_precision_integers.ll
@@ -8,6 +8,14 @@ define i13 @getConstantI13() {
ret i13 42
}
+define i96 @getConstantI96() {
+ ret i96 18446744073709551620
+}
+
+define i160 @getConstantI160() {
+ ret i160 3363637389930338837376336738763689377839373638
+}
+
;; Capabilities:
; CHECK-DAG: OpExtension "SPV_ALTERA_arbitrary_precision_integers"
; CHECK-DAG: OpCapability ArbitraryPrecisionIntegersALTERA
@@ -17,14 +25,20 @@ define i13 @getConstantI13() {
;; Names:
; CHECK-DAG: OpName %[[#GET_I6:]] "getConstantI6"
; CHECK-DAG: OpName %[[#GET_I13:]] "getConstantI13"
+; CHECK-DAG: OpName %[[#GET_I96:]] "getConstantI96"
+; CHECK-DAG: OpName %[[#GET_I160:]] "getConstantI160"
; CHECK-NOT: DAG-FENCE
;; Types and Constants:
; CHECK-DAG: %[[#I6:]] = OpTypeInt 6 0
; CHECK-DAG: %[[#I13:]] = OpTypeInt 13 0
+; CHECK-DAG: %[[#I96:]] = OpTypeInt 96 0
+; CHECK-DAG: %[[#I160:]] = OpTypeInt 160 0
; CHECK-DAG: %[[#CST_I6:]] = OpConstant %[[#I6]] 2
; CHECK-DAG: %[[#CST_I13:]] = OpConstant %[[#I13]] 42
+; CHECK-DAG: %[[#CST_I96:]] = OpConstant %[[#I96]] 18446744073709551620
+; CHECK-DAG: %[[#CST_I160:]] = OpConstant %[[#I160]] 3363637389930338837376336738763689377839373638
; CHECK: %[[#GET_I6]] = OpFunction %[[#I6]]
; CHECK: OpReturnValue %[[#CST_I6]]
@@ -33,3 +47,11 @@ define i13 @getConstantI13() {
; CHECK: %[[#GET_I13]] = OpFunction %[[#I13]]
; CHECK: OpReturnValue %[[#CST_I13]]
; CHECK: OpFunctionEnd
+
+; CHECK: %[[#GET_I96]] = OpFunction %[[#I96]]
+; CHECK: OpReturnValue %[[#CST_I96]]
+; CHECK: OpFunctionEnd
+
+; CHECK: %[[#GET_I160]] = OpFunction %[[#I160]]
+; CHECK: OpReturnValue %[[#CST_I160]]
+; CHECK: OpFunctionEnd
>From 9a67c5cacdd0d70160fc44859885c9683070860a Mon Sep 17 00:00:00 2001
From: "yixing.zhang" <yixingzh at smtp.igk.intel.com>
Date: Fri, 6 Mar 2026 20:52:35 +0100
Subject: [PATCH 2/6] fix instruction printer
---
llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVInstPrinter.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVInstPrinter.cpp b/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVInstPrinter.cpp
index 498f0255ae4eb..3f534a9497677 100644
--- a/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVInstPrinter.cpp
+++ b/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVInstPrinter.cpp
@@ -59,7 +59,7 @@ void SPIRVInstPrinter::printOpConstantVarOps(const MCInst *MI,
uint64_t Word = MI->getOperand(StartIndex + i).getImm();
Val |= APInt(TotalBits, Word) << (i * 32);
}
- O << Val;
+ O << ' ' << Val;
return;
}
>From 632d7795a4b3df7be0873c413f0a2eb0df68f2a4 Mon Sep 17 00:00:00 2001
From: "yixing.zhang" <yixingzh at smtp.igk.intel.com>
Date: Fri, 6 Mar 2026 21:47:08 +0100
Subject: [PATCH 3/6] update test
---
llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp | 19 ++++++-------------
llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h | 2 +-
...SPV_ALTERA_arbitrary_precision_integers.ll | 2 +-
.../apint-constant.ll | 16 ++++++++--------
4 files changed, 16 insertions(+), 23 deletions(-)
diff --git a/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp b/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
index 5ee0f71099f06..9a85634c82626 100644
--- a/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
@@ -153,8 +153,6 @@ SPIRVTypeInst SPIRVGlobalRegistry::getOpTypeBool(MachineIRBuilder &MIRBuilder) {
unsigned SPIRVGlobalRegistry::adjustOpTypeIntWidth(unsigned Width) const {
const SPIRVSubtarget &ST = cast<SPIRVSubtarget>(CurMF->getSubtarget());
- if (Width > 1024)
- report_fatal_error("Unsupported integer width!");
if (ST.canUseExtension(
SPIRV::Extension::SPV_ALTERA_arbitrary_precision_integers) ||
(Width == 4 && ST.canUseExtension(SPIRV::Extension::SPV_INTEL_int4)))
@@ -169,7 +167,7 @@ unsigned SPIRVGlobalRegistry::adjustOpTypeIntWidth(unsigned Width) const {
return 64;
else if (Width <= 128)
return 128;
- return Width;
+ reportFatalUsageError("Unsupported Integer width!");
}
SPIRVTypeInst SPIRVGlobalRegistry::getOpTypeInt(unsigned Width,
@@ -408,7 +406,7 @@ Register SPIRVGlobalRegistry::getOrCreateConstInt(const APInt &Val,
return createConstInt(CI, I, SpvType, TII, ZeroAsNull);
}
-Register SPIRVGlobalRegistry::createConstInt(const Constant *CA,
+Register SPIRVGlobalRegistry::createConstInt(const ConstantInt *CI,
MachineInstr &I,
SPIRVTypeInst SpvType,
const SPIRVInstrInfo &TII,
@@ -427,20 +425,15 @@ Register SPIRVGlobalRegistry::createConstInt(const Constant *CA,
MachineInstrBuilder MIB;
if (BitWidth == 1) {
MIB = MIRBuilder
- .buildInstr(CA->isNegativeZeroValue() ? SPIRV::OpConstantFalse
+ .buildInstr(CI->isZero() ? SPIRV::OpConstantFalse
: SPIRV::OpConstantTrue)
.addDef(Res)
.addUse(getSPIRVTypeID(SpvType));
- } else if (!CA->isNegativeZeroValue() || !ZeroAsNull) {
+ } else if (!CI->isZero() || !ZeroAsNull) {
MIB = MIRBuilder.buildInstr(SPIRV::OpConstantI)
.addDef(Res)
.addUse(getSPIRVTypeID(SpvType));
- if (BitWidth <= 64) {
- const ConstantInt *CI = dyn_cast<ConstantInt>(CA);
- addNumImm(APInt(BitWidth, CI->getZExtValue()), MIB);
- } else {
- addNumImm(CA->getUniqueInteger(), MIB);
- }
+ addNumImm(CI->getValue(), MIB);
} else {
MIB = MIRBuilder.buildInstr(SPIRV::OpConstantNull)
.addDef(Res)
@@ -452,7 +445,7 @@ Register SPIRVGlobalRegistry::createConstInt(const Constant *CA,
*ST.getRegBankInfo());
return MIB;
});
- add(CA, Const);
+ add(CI, Const);
return Res;
}
diff --git a/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h b/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h
index bd9bdfa759961..7296f2c0bf351 100644
--- a/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h
+++ b/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h
@@ -531,7 +531,7 @@ class SPIRVGlobalRegistry : public SPIRVIRMapping {
Register getOrCreateConstInt(const APInt &Val, MachineInstr &I,
SPIRVTypeInst SpvType, const SPIRVInstrInfo &TII,
bool ZeroAsNull = true);
- Register createConstInt(const Constant *CA, MachineInstr &I,
+ Register createConstInt(const ConstantInt *CI, MachineInstr &I,
SPIRVTypeInst SpvType, const SPIRVInstrInfo &TII,
bool ZeroAsNull);
Register getOrCreateConstFP(APFloat Val, MachineInstr &I,
diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_ALTERA_arbitrary_precision_integers/SPV_ALTERA_arbitrary_precision_integers.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_ALTERA_arbitrary_precision_integers/SPV_ALTERA_arbitrary_precision_integers.ll
index a0451278f82cd..62c2374103738 100644
--- a/llvm/test/CodeGen/SPIRV/extensions/SPV_ALTERA_arbitrary_precision_integers/SPV_ALTERA_arbitrary_precision_integers.ll
+++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_ALTERA_arbitrary_precision_integers/SPV_ALTERA_arbitrary_precision_integers.ll
@@ -54,4 +54,4 @@ define i160 @getConstantI160() {
; CHECK: %[[#GET_I160]] = OpFunction %[[#I160]]
; CHECK: OpReturnValue %[[#CST_I160]]
-; CHECK: OpFunctionEnd
+; CHECK: OpFunctionEnd
\ No newline at end of file
diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_ALTERA_arbitrary_precision_integers/apint-constant.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_ALTERA_arbitrary_precision_integers/apint-constant.ll
index 6ed6228653ff5..6935afdf9f44b 100644
--- a/llvm/test/CodeGen/SPIRV/extensions/SPV_ALTERA_arbitrary_precision_integers/apint-constant.ll
+++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_ALTERA_arbitrary_precision_integers/apint-constant.ll
@@ -6,15 +6,15 @@
; CHECK-DAG: %[[#INT128:]] = OpTypeInt 128 0
; CHECK-DAG: %[[#INT96:]] = OpTypeInt 96 0
; CHECK-DAG: %[[#INT97:]] = OpTypeInt 97 0
-; CHECK-DAG: %[[#NEG128:]] = OpConstant %[[#INT128]] 4294965247 4294967295 4294967295 4294967295
-; CHECK-DAG: %[[#ONE128:]] = OpConstant %[[#INT128]] 1 0 0 0
-; CHECK-DAG: %[[#BOUNDARY:]] = OpConstant %[[#INT128]] 4294967295 4294967295 0 0
+; CHECK-DAG: %[[#BOUNDARY:]] = OpConstant %[[#INT128]] 18446744073709551615
+; CHECK-DAG: %[[#ONE128:]] = OpConstant %[[#INT128]] 1
+; CHECK-DAG: %[[#NEG128:]] = OpConstant %[[#INT128]] -2049
; CHECK-DAG: %[[#ZERO128:]] = OpConstantNull %[[#INT128]]
-; CHECK-DAG: %[[#NEG96:]] = OpConstant %[[#INT96]] 4294967295 4294967295 4294967295
-; CHECK-DAG: %[[#OVER64:]] = OpConstant %[[#INT96]] 1 0 1
-; CHECK-DAG: %[[#NEG97:]] = OpConstant %[[#INT97]] 4294967295 4294967295 4294967295 1
-; CHECK-DAG: %[[#OVER64_I97:]] = OpConstant %[[#INT97]] 1 0 1 0
-; CHECK-DAG: %[[#I97_MAX:]] = OpConstant %[[#INT97]] 0 0 0 1
+; CHECK-DAG: %[[#OVER64:]] = OpConstant %[[#INT96]] 18446744073709551617
+; CHECK-DAG: %[[#NEG96:]] = OpConstant %[[#INT96]] -1
+; CHECK-DAG: %[[#I97_MAX:]] = OpConstant %[[#INT97]] 79228162514264337593543950336
+; CHECK-DAG: %[[#OVER64_I97:]] = OpConstant %[[#INT97]] 18446744073709551617
+; CHECK-DAG: %[[#NEG97:]] = OpConstant %[[#INT97]] 158456325028528675187087900671
; CHECK: OpStore %[[#]] %[[#NEG128]] Aligned 16
; CHECK: OpStore %[[#]] %[[#ONE128]] Aligned 16
>From 52a882e783f743cd54dff22619ebbc8011fa5d44 Mon Sep 17 00:00:00 2001
From: "yixing.zhang" <yixingzh at smtp.igk.intel.com>
Date: Sun, 8 Mar 2026 18:22:43 +0100
Subject: [PATCH 4/6] add support for integer that is not a multiply of 32
---
.../SPIRV/MCTargetDesc/SPIRVInstPrinter.cpp | 22 ++++++++++++++++++-
.../SPIRV/MCTargetDesc/SPIRVInstPrinter.h | 2 ++
...SPV_ALTERA_arbitrary_precision_integers.ll | 2 +-
.../apint-constant.ll | 6 ++---
.../i128-addsub.ll | 2 +-
5 files changed, 28 insertions(+), 6 deletions(-)
diff --git a/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVInstPrinter.cpp b/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVInstPrinter.cpp
index 3f534a9497677..783bef659e326 100644
--- a/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVInstPrinter.cpp
+++ b/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVInstPrinter.cpp
@@ -51,6 +51,16 @@ void SPIRVInstPrinter::printOpConstantVarOps(const MCInst *MI,
const unsigned NumVarOps = MI->getNumOperands() - StartIndex;
if (MI->getOpcode() == SPIRV::OpConstantI && NumVarOps > 2) {
+ // Look up the actual bitwidth of this int type register from IntTypeBitwidths map
+ unsigned IntTypeRegId = getIDFromRegister(MI->getOperand(1).getReg().id());
+ auto IntTypeRegIt = IntTypeBitwidths.find(IntTypeRegId);
+ if(IntTypeRegIt == IntTypeBitwidths.end()) {
+ // In valid SPIR-V, types are always defined before use.
+ llvm_unreachable("Int type register with ID " + std::to_string(IntTypeRegId) +
+ " is used before defined in OpTypeInt");
+ }
+ int Bitwidth = IntTypeRegIt->second;
+
// SPV_ALTERA_arbitrary_precision_integers allows for integer widths greater
// than 64, which will be encoded via multiple operands.
const unsigned TotalBits = NumVarOps * 32;
@@ -59,7 +69,8 @@ void SPIRVInstPrinter::printOpConstantVarOps(const MCInst *MI,
uint64_t Word = MI->getOperand(StartIndex + i).getImm();
Val |= APInt(TotalBits, Word) << (i * 32);
}
- O << ' ' << Val;
+ APInt ActualVal = Val.trunc(Bitwidth);
+ O << ' ' << ActualVal;
return;
}
@@ -106,6 +117,12 @@ void SPIRVInstPrinter::printOpConstantVarOps(const MCInst *MI,
O << Imm;
}
+void SPIRVInstPrinter::recordIntType(const MCInst *MI) {
+ unsigned ResultID = getIDFromRegister(MI->getOperand(0).getReg().id());
+ unsigned Bitwidth = MI->getOperand(1).getImm();
+ IntTypeBitwidths[ResultID] = Bitwidth;
+}
+
void SPIRVInstPrinter::recordOpExtInstImport(const MCInst *MI) {
MCRegister Reg = MI->getOperand(0).getReg();
auto Name = getSPIRVStringOperand(*MI, 1);
@@ -118,6 +135,9 @@ void SPIRVInstPrinter::printInst(const MCInst *MI, uint64_t Address,
raw_ostream &OS) {
const unsigned OpCode = MI->getOpcode();
printInstruction(MI, Address, OS);
+ if(OpCode == SPIRV::OpTypeInt){
+ recordIntType(MI);
+ }
if (OpCode == SPIRV::OpDecorate) {
printOpDecorate(MI, OS);
diff --git a/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVInstPrinter.h b/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVInstPrinter.h
index 8f2ad48efa9d7..f90af3bbcdc3f 100644
--- a/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVInstPrinter.h
+++ b/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVInstPrinter.h
@@ -22,7 +22,9 @@ namespace llvm {
class SPIRVInstPrinter : public MCInstPrinter {
private:
SmallDenseMap<MCRegister, SPIRV::InstructionSet::InstructionSet> ExtInstSetIDs;
+ SmallDenseMap<unsigned, unsigned> IntTypeBitwidths;
void recordOpExtInstImport(const MCInst *MI);
+ void recordIntType(const MCInst *MI);
public:
using MCInstPrinter::MCInstPrinter;
diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_ALTERA_arbitrary_precision_integers/SPV_ALTERA_arbitrary_precision_integers.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_ALTERA_arbitrary_precision_integers/SPV_ALTERA_arbitrary_precision_integers.ll
index 62c2374103738..a0451278f82cd 100644
--- a/llvm/test/CodeGen/SPIRV/extensions/SPV_ALTERA_arbitrary_precision_integers/SPV_ALTERA_arbitrary_precision_integers.ll
+++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_ALTERA_arbitrary_precision_integers/SPV_ALTERA_arbitrary_precision_integers.ll
@@ -54,4 +54,4 @@ define i160 @getConstantI160() {
; CHECK: %[[#GET_I160]] = OpFunction %[[#I160]]
; CHECK: OpReturnValue %[[#CST_I160]]
-; CHECK: OpFunctionEnd
\ No newline at end of file
+; CHECK: OpFunctionEnd
diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_ALTERA_arbitrary_precision_integers/apint-constant.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_ALTERA_arbitrary_precision_integers/apint-constant.ll
index 6935afdf9f44b..3a5c4f02fa879 100644
--- a/llvm/test/CodeGen/SPIRV/extensions/SPV_ALTERA_arbitrary_precision_integers/apint-constant.ll
+++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_ALTERA_arbitrary_precision_integers/apint-constant.ll
@@ -12,9 +12,9 @@
; CHECK-DAG: %[[#ZERO128:]] = OpConstantNull %[[#INT128]]
; CHECK-DAG: %[[#OVER64:]] = OpConstant %[[#INT96]] 18446744073709551617
; CHECK-DAG: %[[#NEG96:]] = OpConstant %[[#INT96]] -1
-; CHECK-DAG: %[[#I97_MAX:]] = OpConstant %[[#INT97]] 79228162514264337593543950336
+; CHECK-DAG: %[[#I97_MAX:]] = OpConstant %[[#INT97]] 79228162514264337593543950335
; CHECK-DAG: %[[#OVER64_I97:]] = OpConstant %[[#INT97]] 18446744073709551617
-; CHECK-DAG: %[[#NEG97:]] = OpConstant %[[#INT97]] 158456325028528675187087900671
+; CHECK-DAG: %[[#NEG97:]] = OpConstant %[[#INT97]] -1
; CHECK: OpStore %[[#]] %[[#NEG128]] Aligned 16
; CHECK: OpStore %[[#]] %[[#ONE128]] Aligned 16
@@ -48,6 +48,6 @@ define spir_func void @test_i97_const(ptr addrspace(4) %p) addrspace(4) {
entry:
store i97 -1, ptr addrspace(4) %p, align 16
store i97 18446744073709551617, ptr addrspace(4) %p, align 16
- store i97 79228162514264337593543950336, ptr addrspace(4) %p, align 16
+ store i97 79228162514264337593543950335, ptr addrspace(4) %p, align 16
ret void
}
diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_ALTERA_arbitrary_precision_integers/i128-addsub.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_ALTERA_arbitrary_precision_integers/i128-addsub.ll
index c90ffdd17996c..f733c8f9ce09b 100644
--- a/llvm/test/CodeGen/SPIRV/extensions/SPV_ALTERA_arbitrary_precision_integers/i128-addsub.ll
+++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_ALTERA_arbitrary_precision_integers/i128-addsub.ll
@@ -10,7 +10,7 @@
; CHECK: OpName %[[#TestAdd:]] "test_add"
; CHECK: OpName %[[#TestSub:]] "test_sub"
; CHECK: %[[#Int128Ty:]] = OpTypeInt 128 0
-; CHECK: %[[#Const64Int128:]] = OpConstant %[[#Int128Ty]] 64 0 0 0
+; CHECK: %[[#Const64Int128:]] = OpConstant %[[#Int128Ty]] 64
; CHECK: %[[#TestAdd]] = OpFunction
define spir_func void @test_add(i64 %AL, i64 %AH, i64 %BL, i64 %BH, ptr %RL, ptr %RH) {
>From 0245083ef04ecfde67e7d5ad9940a52b81c6f3e4 Mon Sep 17 00:00:00 2001
From: "yixing.zhang" <yixingzh at smtp.igk.intel.com>
Date: Sun, 8 Mar 2026 18:27:05 +0100
Subject: [PATCH 5/6] code clean up
---
llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVInstPrinter.cpp | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVInstPrinter.cpp b/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVInstPrinter.cpp
index 783bef659e326..4ecad632ff5ab 100644
--- a/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVInstPrinter.cpp
+++ b/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVInstPrinter.cpp
@@ -55,9 +55,7 @@ void SPIRVInstPrinter::printOpConstantVarOps(const MCInst *MI,
unsigned IntTypeRegId = getIDFromRegister(MI->getOperand(1).getReg().id());
auto IntTypeRegIt = IntTypeBitwidths.find(IntTypeRegId);
if(IntTypeRegIt == IntTypeBitwidths.end()) {
- // In valid SPIR-V, types are always defined before use.
- llvm_unreachable("Int type register with ID " + std::to_string(IntTypeRegId) +
- " is used before defined in OpTypeInt");
+ llvm_unreachable("Int type register used before defined in OpTypeInt");
}
int Bitwidth = IntTypeRegIt->second;
>From 4bf2a71a12332d49228c052be537a40785eb52d0 Mon Sep 17 00:00:00 2001
From: "yixing.zhang" <yixingzh at smtp.igk.intel.com>
Date: Sun, 8 Mar 2026 19:04:50 +0100
Subject: [PATCH 6/6] code clean up
---
llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVInstPrinter.cpp | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVInstPrinter.cpp b/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVInstPrinter.cpp
index 4ecad632ff5ab..d01a2706467e2 100644
--- a/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVInstPrinter.cpp
+++ b/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVInstPrinter.cpp
@@ -116,9 +116,9 @@ void SPIRVInstPrinter::printOpConstantVarOps(const MCInst *MI,
}
void SPIRVInstPrinter::recordIntType(const MCInst *MI) {
- unsigned ResultID = getIDFromRegister(MI->getOperand(0).getReg().id());
+ unsigned IntTypeRegId = getIDFromRegister(MI->getOperand(0).getReg().id());
unsigned Bitwidth = MI->getOperand(1).getImm();
- IntTypeBitwidths[ResultID] = Bitwidth;
+ IntTypeBitwidths[IntTypeRegId] = Bitwidth;
}
void SPIRVInstPrinter::recordOpExtInstImport(const MCInst *MI) {
@@ -133,7 +133,7 @@ void SPIRVInstPrinter::printInst(const MCInst *MI, uint64_t Address,
raw_ostream &OS) {
const unsigned OpCode = MI->getOpcode();
printInstruction(MI, Address, OS);
- if(OpCode == SPIRV::OpTypeInt){
+ if(OpCode == SPIRV::OpTypeInt) {
recordIntType(MI);
}
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