[llvm] [NewPM] Add port for aarch64-simd-scalar (PR #185256)
via llvm-commits
llvm-commits at lists.llvm.org
Sat Mar 7 22:56:28 PST 2026
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-aarch64
Author: Anshul Nigham (nigham)
<details>
<summary>Changes</summary>
---
Full diff: https://github.com/llvm/llvm-project/pull/185256.diff
4 Files Affected:
- (modified) llvm/lib/Target/AArch64/AArch64.h (+8-1)
- (modified) llvm/lib/Target/AArch64/AArch64AdvSIMDScalarPass.cpp (+38-17)
- (modified) llvm/lib/Target/AArch64/AArch64PassRegistry.def (+1)
- (modified) llvm/lib/Target/AArch64/AArch64TargetMachine.cpp (+1-1)
``````````diff
diff --git a/llvm/lib/Target/AArch64/AArch64.h b/llvm/lib/Target/AArch64/AArch64.h
index d8d2445d085c0..194f1858d94e1 100644
--- a/llvm/lib/Target/AArch64/AArch64.h
+++ b/llvm/lib/Target/AArch64/AArch64.h
@@ -82,7 +82,7 @@ ModulePass *createAArch64Arm64ECCallLoweringPass();
void initializeAArch64A53Fix835769LegacyPass(PassRegistry &);
void initializeAArch64A57FPLoadBalancingPass(PassRegistry&);
-void initializeAArch64AdvSIMDScalarPass(PassRegistry&);
+void initializeAArch64AdvSIMDScalarLegacyPass(PassRegistry &);
void initializeAArch64AsmPrinterPass(PassRegistry &);
void initializeAArch64PointerAuthPass(PassRegistry&);
void initializeAArch64BranchTargetsPass(PassRegistry&);
@@ -135,6 +135,13 @@ class AArch64A53Fix835769Pass : public PassInfoMixin<AArch64A53Fix835769Pass> {
MachineFunctionAnalysisManager &MFAM);
};
+class AArch64AdvSIMDScalarPass
+ : public PassInfoMixin<AArch64AdvSIMDScalarPass> {
+public:
+ PreservedAnalyses run(MachineFunction &MF,
+ MachineFunctionAnalysisManager &MFAM);
+};
+
} // end namespace llvm
#endif
diff --git a/llvm/lib/Target/AArch64/AArch64AdvSIMDScalarPass.cpp b/llvm/lib/Target/AArch64/AArch64AdvSIMDScalarPass.cpp
index c85adcf85f8dc..8f5bec4ac8fa5 100644
--- a/llvm/lib/Target/AArch64/AArch64AdvSIMDScalarPass.cpp
+++ b/llvm/lib/Target/AArch64/AArch64AdvSIMDScalarPass.cpp
@@ -62,9 +62,9 @@ STATISTIC(NumCopiesInserted, "Number of cross-class copies inserted");
#define AARCH64_ADVSIMD_NAME "AdvSIMD Scalar Operation Optimization"
namespace {
-class AArch64AdvSIMDScalar : public MachineFunctionPass {
- MachineRegisterInfo *MRI;
- const TargetInstrInfo *TII;
+class AArch64AdvSIMDScalarImpl {
+public:
+ bool run(MachineFunction &MF);
private:
// isProfitableToTransform - Predicate function to determine whether an
@@ -80,9 +80,14 @@ class AArch64AdvSIMDScalar : public MachineFunctionPass {
// processMachineBasicBlock - Main optimization loop.
bool processMachineBasicBlock(MachineBasicBlock *MBB);
+ MachineRegisterInfo *MRI;
+ const TargetInstrInfo *TII;
+};
+
+class AArch64AdvSIMDScalarLegacy : public MachineFunctionPass {
public:
static char ID; // Pass identification, replacement for typeid.
- explicit AArch64AdvSIMDScalar() : MachineFunctionPass(ID) {}
+ explicit AArch64AdvSIMDScalarLegacy() : MachineFunctionPass(ID) {}
bool runOnMachineFunction(MachineFunction &F) override;
@@ -93,12 +98,23 @@ class AArch64AdvSIMDScalar : public MachineFunctionPass {
MachineFunctionPass::getAnalysisUsage(AU);
}
};
-char AArch64AdvSIMDScalar::ID = 0;
+char AArch64AdvSIMDScalarLegacy::ID = 0;
} // end anonymous namespace
-INITIALIZE_PASS(AArch64AdvSIMDScalar, "aarch64-simd-scalar",
+INITIALIZE_PASS(AArch64AdvSIMDScalarLegacy, "aarch64-simd-scalar",
AARCH64_ADVSIMD_NAME, false, false)
+PreservedAnalyses
+AArch64AdvSIMDScalarPass::run(MachineFunction &MF,
+ MachineFunctionAnalysisManager &MFAM) {
+ const bool Changed = AArch64AdvSIMDScalarImpl().run(MF);
+ if (!Changed)
+ return PreservedAnalyses::all();
+ PreservedAnalyses PA = getMachineFunctionPassPreservedAnalyses();
+ PA.preserveSet<CFGAnalyses>();
+ return PA;
+}
+
static bool isGPR64(unsigned Reg, unsigned SubReg,
const MachineRegisterInfo *MRI) {
if (SubReg)
@@ -187,7 +203,7 @@ static bool isTransformable(const MachineInstr &MI) {
// isProfitableToTransform - Predicate function to determine whether an
// instruction should be transformed to its equivalent AdvSIMD scalar
// instruction. "add Xd, Xn, Xm" ==> "add Dd, Da, Db", for example.
-bool AArch64AdvSIMDScalar::isProfitableToTransform(
+bool AArch64AdvSIMDScalarImpl::isProfitableToTransform(
const MachineInstr &MI) const {
// If this instruction isn't eligible to be transformed (no SIMD equivalent),
// early exit since that's the common case.
@@ -282,7 +298,7 @@ static MachineInstr *insertCopy(const TargetInstrInfo *TII, MachineInstr &MI,
// transformInstruction - Perform the transformation of an instruction
// to its equivalent AdvSIMD scalar instruction. Update inputs and outputs
// to be the correct register class, minimizing cross-class copies.
-void AArch64AdvSIMDScalar::transformInstruction(MachineInstr &MI) {
+void AArch64AdvSIMDScalarImpl::transformInstruction(MachineInstr &MI) {
LLVM_DEBUG(dbgs() << "Scalar transform: " << MI);
MachineBasicBlock *MBB = MI.getParent();
@@ -373,7 +389,8 @@ void AArch64AdvSIMDScalar::transformInstruction(MachineInstr &MI) {
}
// processMachineBasicBlock - Main optimization loop.
-bool AArch64AdvSIMDScalar::processMachineBasicBlock(MachineBasicBlock *MBB) {
+bool AArch64AdvSIMDScalarImpl::processMachineBasicBlock(
+ MachineBasicBlock *MBB) {
bool Changed = false;
for (MachineInstr &MI : llvm::make_early_inc_range(*MBB)) {
if (isProfitableToTransform(MI)) {
@@ -385,18 +402,22 @@ bool AArch64AdvSIMDScalar::processMachineBasicBlock(MachineBasicBlock *MBB) {
}
// runOnMachineFunction - Pass entry point from PassManager.
-bool AArch64AdvSIMDScalar::runOnMachineFunction(MachineFunction &mf) {
- bool Changed = false;
- LLVM_DEBUG(dbgs() << "***** AArch64AdvSIMDScalar *****\n");
-
+bool AArch64AdvSIMDScalarLegacy::runOnMachineFunction(MachineFunction &mf) {
if (skipFunction(mf.getFunction()))
return false;
- MRI = &mf.getRegInfo();
- TII = mf.getSubtarget().getInstrInfo();
+ return AArch64AdvSIMDScalarImpl().run(mf);
+}
+
+bool AArch64AdvSIMDScalarImpl::run(MachineFunction &MF) {
+ bool Changed = false;
+ LLVM_DEBUG(dbgs() << "***** AArch64AdvSIMDScalar *****\n");
+
+ MRI = &MF.getRegInfo();
+ TII = MF.getSubtarget().getInstrInfo();
// Just check things on a one-block-at-a-time basis.
- for (MachineBasicBlock &MBB : mf)
+ for (MachineBasicBlock &MBB : MF)
if (processMachineBasicBlock(&MBB))
Changed = true;
return Changed;
@@ -405,5 +426,5 @@ bool AArch64AdvSIMDScalar::runOnMachineFunction(MachineFunction &mf) {
// createAArch64AdvSIMDScalar - Factory function used by AArch64TargetMachine
// to add the pass to the PassManager.
FunctionPass *llvm::createAArch64AdvSIMDScalar() {
- return new AArch64AdvSIMDScalar();
+ return new AArch64AdvSIMDScalarLegacy();
}
diff --git a/llvm/lib/Target/AArch64/AArch64PassRegistry.def b/llvm/lib/Target/AArch64/AArch64PassRegistry.def
index 6c12ee3469d5c..e3df958fd7329 100644
--- a/llvm/lib/Target/AArch64/AArch64PassRegistry.def
+++ b/llvm/lib/Target/AArch64/AArch64PassRegistry.def
@@ -28,4 +28,5 @@
#endif
MACHINE_FUNCTION_PASS("aarch64-fix-cortex-a53-835769", AArch64A53Fix835769Pass())
MACHINE_FUNCTION_PASS("aarch64-ldst-opt", AArch64LoadStoreOptPass())
+MACHINE_FUNCTION_PASS("aarch64-simd-scalar", AArch64AdvSIMDScalarPass())
#undef MACHINE_FUNCTION_PASS
diff --git a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
index 294ea6c53ad4a..e9cd1e9e64aba 100644
--- a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
+++ b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
@@ -245,7 +245,7 @@ LLVMInitializeAArch64Target() {
initializeGlobalISel(PR);
initializeAArch64A53Fix835769LegacyPass(PR);
initializeAArch64A57FPLoadBalancingPass(PR);
- initializeAArch64AdvSIMDScalarPass(PR);
+ initializeAArch64AdvSIMDScalarLegacyPass(PR);
initializeAArch64AsmPrinterPass(PR);
initializeAArch64BranchTargetsPass(PR);
initializeAArch64CollectLOHPass(PR);
``````````
</details>
https://github.com/llvm/llvm-project/pull/185256
More information about the llvm-commits
mailing list