[llvm] [SelectionDAG] Second SimplifyDemandedBits pass for AND RHS using LHS known zeros (scalar only) (PR #185235)

[Craig Topper via llvm-commits]

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@@ -1513,6 +1513,18 @@ bool TargetLowering::SimplifyDemandedBits(
                              Known2, TLO, Depth + 1))
       return true;
 
+    // FIXME: Pretty much all these extra conditions are to avoid regressions in
+    // x86 and AMDGPU.
+    unsigned Op1Opc = Op1.getOpcode();
+    if (!VT.isVector() &&
+        (Op1Opc == ISD::ZERO_EXTEND || Op1Opc == ISD::SIGN_EXTEND ||
+         Op1Opc == ISD::ANY_EXTEND || Op1Opc == ISD::TRUNCATE) &&
+        Op1.getOperand(0).getScalarValueSizeInBits() != 1 &&
+        (~Known2.Zero & DemandedBits) != DemandedBits &&
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topperc wrote:

I don't we can use Known2.Zero here. It was created using `~Known.Zero & DemandedBits` as the DemandedBits. That means the KnownBits are unreliable for any bits where Op1 has zeros. We can't then use that op to optimize Op1.

https://github.com/llvm/llvm-project/pull/185235