[llvm] [SelectionDAG] Second SimplifyDemandedBits pass for AND RHS using LHS known zeros (scalar only) (PR #185235)

[via llvm-commits]

SiliconA-Z wrote:

@RKSimon @topperc This is what I need to merge so I can merge https://github.com/llvm/llvm-project/pull/157687#issuecomment-4017546894

https://github.com/llvm/llvm-project/pull/185235