[llvm] [SelectionDAG] Second SimplifyDemandedBits pass for AND RHS using LHS known zeros (scalar only) (PR #185235)

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``````````bash
git-clang-format --diff origin/main HEAD --extensions cpp -- llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp --diff_from_common_commit
``````````

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``````````diff
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 507567d63..cbf8ccc4f 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -1513,7 +1513,8 @@ bool TargetLowering::SimplifyDemandedBits(
                              Known2, TLO, Depth + 1))
       return true;
 
-    // FIXME: Pretty much all these extra conditions are to avoid regressions in x86 tests.
+    // FIXME: Pretty much all these extra conditions are to avoid regressions in
+    // x86 tests.
     if ((~Known2.Zero & DemandedBits) != DemandedBits) {
       unsigned Op1Opc = Op1.getOpcode();
       if (!VT.isVector() &&

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https://github.com/llvm/llvm-project/pull/185235