[llvm] [Analysis] isTriviallyVectorizable - add Intrinsic::clmul along with vectorisation tests (PR #180014)
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Sat Mar 7 01:51:33 PST 2026
https://github.com/RKSimon updated https://github.com/llvm/llvm-project/pull/180014
>From d42070d105b567431fc574302947335cc4618aa7 Mon Sep 17 00:00:00 2001
From: pranshoe <pranshu.goyal71 at gmail.com>
Date: Thu, 5 Feb 2026 19:17:06 +0000
Subject: [PATCH 1/8] [Analysis] isTriviallyVectorizable - add Intrinsic::clmul
along with vectorisation tests
---
llvm/lib/Analysis/VectorUtils.cpp | 1 +
llvm/test/Transforms/LoopVectorize/clmul.ll | 136 ++++++++++++++++++++
2 files changed, 137 insertions(+)
create mode 100644 llvm/test/Transforms/LoopVectorize/clmul.ll
diff --git a/llvm/lib/Analysis/VectorUtils.cpp b/llvm/lib/Analysis/VectorUtils.cpp
index d4083c49626fe..f7055dbde275b 100644
--- a/llvm/lib/Analysis/VectorUtils.cpp
+++ b/llvm/lib/Analysis/VectorUtils.cpp
@@ -122,6 +122,7 @@ bool llvm::isTriviallyVectorizable(Intrinsic::ID ID) {
case Intrinsic::llrint:
case Intrinsic::ucmp:
case Intrinsic::scmp:
+ case Intrinsic::clmul:
return true;
default:
return false;
diff --git a/llvm/test/Transforms/LoopVectorize/clmul.ll b/llvm/test/Transforms/LoopVectorize/clmul.ll
new file mode 100644
index 0000000000000..c0102ba5a4034
--- /dev/null
+++ b/llvm/test/Transforms/LoopVectorize/clmul.ll
@@ -0,0 +1,136 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
+; RUN: opt -passes=loop-vectorize -mtriple=x86_64 -mattr=+pclmul -S %s | FileCheck %s --check-prefix=X86
+; RUN: opt -passes=loop-vectorize -mtriple=aarch64 -mattr=+crypto -S %s | FileCheck %s --check-prefix=ARM
+; RUN: opt -passes=loop-vectorize -mtriple=riscv64 -mattr=+v -S %s | FileCheck %s --check-prefix=RISCV
+
+declare i64 @llvm.clmul.i64(i64 %a, i64 %b)
+
+define void @clmul_loop(ptr %a, ptr %b, ptr %c, i64 %n) {
+; X86-LABEL: define void @clmul_loop(
+; X86-SAME: ptr [[A:%.*]], ptr [[B:%.*]], ptr [[C:%.*]], i64 [[N:%.*]]) #[[ATTR1:[0-9]+]] {
+; X86-NEXT: [[ENTRY:.*]]:
+; X86-NEXT: [[B3:%.*]] = ptrtoint ptr [[B]] to i64
+; X86-NEXT: [[A2:%.*]] = ptrtoint ptr [[A]] to i64
+; X86-NEXT: [[C1:%.*]] = ptrtoint ptr [[C]] to i64
+; X86-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 8
+; X86-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_MEMCHECK:.*]]
+; X86: [[VECTOR_MEMCHECK]]:
+; X86-NEXT: [[TMP0:%.*]] = sub i64 [[C1]], [[A2]]
+; X86-NEXT: [[DIFF_CHECK:%.*]] = icmp ult i64 [[TMP0]], 32
+; X86-NEXT: [[TMP1:%.*]] = sub i64 [[C1]], [[B3]]
+; X86-NEXT: [[DIFF_CHECK4:%.*]] = icmp ult i64 [[TMP1]], 32
+; X86-NEXT: [[CONFLICT_RDX:%.*]] = or i1 [[DIFF_CHECK]], [[DIFF_CHECK4]]
+; X86-NEXT: br i1 [[CONFLICT_RDX]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]
+; X86: [[VECTOR_PH]]:
+; X86-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], 4
+; X86-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]]
+; X86-NEXT: br label %[[VECTOR_BODY:.*]]
+; X86: [[VECTOR_BODY]]:
+; X86-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; X86-NEXT: [[TMP2:%.*]] = getelementptr i64, ptr [[A]], i64 [[INDEX]]
+; X86-NEXT: [[TMP3:%.*]] = getelementptr i64, ptr [[B]], i64 [[INDEX]]
+; X86-NEXT: [[TMP4:%.*]] = getelementptr i64, ptr [[C]], i64 [[INDEX]]
+; X86-NEXT: [[TMP5:%.*]] = getelementptr i64, ptr [[TMP2]], i64 2
+; X86-NEXT: [[WIDE_LOAD:%.*]] = load <2 x i64>, ptr [[TMP2]], align 8
+; X86-NEXT: [[WIDE_LOAD5:%.*]] = load <2 x i64>, ptr [[TMP5]], align 8
+; X86-NEXT: [[TMP6:%.*]] = getelementptr i64, ptr [[TMP3]], i64 2
+; X86-NEXT: [[WIDE_LOAD6:%.*]] = load <2 x i64>, ptr [[TMP3]], align 8
+; X86-NEXT: [[WIDE_LOAD7:%.*]] = load <2 x i64>, ptr [[TMP6]], align 8
+; X86-NEXT: [[TMP7:%.*]] = call <2 x i64> @llvm.clmul.v2i64(<2 x i64> [[WIDE_LOAD]], <2 x i64> [[WIDE_LOAD6]])
+; X86-NEXT: [[TMP8:%.*]] = call <2 x i64> @llvm.clmul.v2i64(<2 x i64> [[WIDE_LOAD5]], <2 x i64> [[WIDE_LOAD7]])
+; X86-NEXT: [[TMP9:%.*]] = getelementptr i64, ptr [[TMP4]], i64 2
+; X86-NEXT: store <2 x i64> [[TMP7]], ptr [[TMP4]], align 8
+; X86-NEXT: store <2 x i64> [[TMP8]], ptr [[TMP9]], align 8
+; X86-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
+; X86-NEXT: [[TMP10:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
+; X86-NEXT: br i1 [[TMP10]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
+; X86: [[MIDDLE_BLOCK]]:
+; X86-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]]
+; X86-NEXT: br i1 [[CMP_N]], label %[[FOR_EXIT:.*]], label %[[SCALAR_PH]]
+; X86: [[SCALAR_PH]]:
+; X86-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_MEMCHECK]] ]
+; X86-NEXT: br label %[[FOR_BODY:.*]]
+; X86: [[FOR_BODY]]:
+; X86-NEXT: [[I:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[I_NEXT:%.*]], %[[FOR_BODY]] ]
+; X86-NEXT: [[PA:%.*]] = getelementptr i64, ptr [[A]], i64 [[I]]
+; X86-NEXT: [[PB:%.*]] = getelementptr i64, ptr [[B]], i64 [[I]]
+; X86-NEXT: [[PC:%.*]] = getelementptr i64, ptr [[C]], i64 [[I]]
+; X86-NEXT: [[VA:%.*]] = load i64, ptr [[PA]], align 8
+; X86-NEXT: [[VB:%.*]] = load i64, ptr [[PB]], align 8
+; X86-NEXT: [[R:%.*]] = call i64 @llvm.clmul.i64(i64 [[VA]], i64 [[VB]])
+; X86-NEXT: store i64 [[R]], ptr [[PC]], align 8
+; X86-NEXT: [[I_NEXT]] = add i64 [[I]], 1
+; X86-NEXT: [[CMP:%.*]] = icmp eq i64 [[I_NEXT]], [[N]]
+; X86-NEXT: br i1 [[CMP]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]
+; X86: [[FOR_EXIT]]:
+; X86-NEXT: ret void
+;
+; ARM-LABEL: define void @clmul_loop(
+; ARM-SAME: ptr [[A:%.*]], ptr [[B:%.*]], ptr [[C:%.*]], i64 [[N:%.*]]) #[[ATTR1:[0-9]+]] {
+; ARM-NEXT: [[ENTRY:.*]]:
+; ARM-NEXT: br label %[[FOR_BODY:.*]]
+; ARM: [[FOR_BODY]]:
+; ARM-NEXT: [[I:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[I_NEXT:%.*]], %[[FOR_BODY]] ]
+; ARM-NEXT: [[PA:%.*]] = getelementptr i64, ptr [[A]], i64 [[I]]
+; ARM-NEXT: [[PB:%.*]] = getelementptr i64, ptr [[B]], i64 [[I]]
+; ARM-NEXT: [[PC:%.*]] = getelementptr i64, ptr [[C]], i64 [[I]]
+; ARM-NEXT: [[VA:%.*]] = load i64, ptr [[PA]], align 8
+; ARM-NEXT: [[VB:%.*]] = load i64, ptr [[PB]], align 8
+; ARM-NEXT: [[R:%.*]] = call i64 @llvm.clmul.i64(i64 [[VA]], i64 [[VB]])
+; ARM-NEXT: store i64 [[R]], ptr [[PC]], align 8
+; ARM-NEXT: [[I_NEXT]] = add i64 [[I]], 1
+; ARM-NEXT: [[CMP:%.*]] = icmp eq i64 [[I_NEXT]], [[N]]
+; ARM-NEXT: br i1 [[CMP]], label %[[FOR_EXIT:.*]], label %[[FOR_BODY]]
+; ARM: [[FOR_EXIT]]:
+; ARM-NEXT: ret void
+;
+; RISCV-LABEL: define void @clmul_loop(
+; RISCV-SAME: ptr [[A:%.*]], ptr [[B:%.*]], ptr [[C:%.*]], i64 [[N:%.*]]) #[[ATTR1:[0-9]+]] {
+; RISCV-NEXT: [[ENTRY:.*]]:
+; RISCV-NEXT: br label %[[FOR_BODY:.*]]
+; RISCV: [[FOR_BODY]]:
+; RISCV-NEXT: [[I:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[I_NEXT:%.*]], %[[FOR_BODY]] ]
+; RISCV-NEXT: [[PA:%.*]] = getelementptr i64, ptr [[A]], i64 [[I]]
+; RISCV-NEXT: [[PB:%.*]] = getelementptr i64, ptr [[B]], i64 [[I]]
+; RISCV-NEXT: [[PC:%.*]] = getelementptr i64, ptr [[C]], i64 [[I]]
+; RISCV-NEXT: [[VA:%.*]] = load i64, ptr [[PA]], align 8
+; RISCV-NEXT: [[VB:%.*]] = load i64, ptr [[PB]], align 8
+; RISCV-NEXT: [[R:%.*]] = call i64 @llvm.clmul.i64(i64 [[VA]], i64 [[VB]])
+; RISCV-NEXT: store i64 [[R]], ptr [[PC]], align 8
+; RISCV-NEXT: [[I_NEXT]] = add i64 [[I]], 1
+; RISCV-NEXT: [[CMP:%.*]] = icmp eq i64 [[I_NEXT]], [[N]]
+; RISCV-NEXT: br i1 [[CMP]], label %[[FOR_EXIT:.*]], label %[[FOR_BODY]]
+; RISCV: [[FOR_EXIT]]:
+; RISCV-NEXT: ret void
+;
+entry:
+ br label %for.body
+
+for.body:
+ %i = phi i64 [0, %entry], [%i.next, %for.body]
+
+ %pa = getelementptr i64, ptr %a, i64 %i
+ %pb = getelementptr i64, ptr %b, i64 %i
+ %pc = getelementptr i64, ptr %c, i64 %i
+
+ %va = load i64, ptr %pa
+ %vb = load i64, ptr %pb
+
+ %r = call i64 @llvm.clmul.i64(i64 %va, i64 %vb)
+
+ store i64 %r, ptr %pc
+
+ %i.next = add i64 %i, 1
+ %cmp = icmp eq i64 %i.next, %n
+ br i1 %cmp, label %for.exit, label %for.body
+
+for.exit:
+ ret void
+
+}
+;.
+; X86: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}
+; X86: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}
+; X86: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}
+; X86: [[LOOP3]] = distinct !{[[LOOP3]], [[META1]]}
+;.
>From 547b9c7915da83dc9e1812c978cb7ed226eb175b Mon Sep 17 00:00:00 2001
From: pranshoe <pranshu.goyal71 at gmail.com>
Date: Fri, 6 Feb 2026 19:38:24 +0000
Subject: [PATCH 2/8] Split Intrinsic::clmul LoopVectorize tests by target
---
.../Transforms/LoopVectorize/AArch64/clmul.ll | 50 +++++++
.../Transforms/LoopVectorize/RISCV/clmul.ll | 50 +++++++
.../Transforms/LoopVectorize/X86/clmul.ll | 96 +++++++++++++
llvm/test/Transforms/LoopVectorize/clmul.ll | 136 ------------------
4 files changed, 196 insertions(+), 136 deletions(-)
create mode 100644 llvm/test/Transforms/LoopVectorize/AArch64/clmul.ll
create mode 100644 llvm/test/Transforms/LoopVectorize/RISCV/clmul.ll
create mode 100644 llvm/test/Transforms/LoopVectorize/X86/clmul.ll
delete mode 100644 llvm/test/Transforms/LoopVectorize/clmul.ll
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/clmul.ll b/llvm/test/Transforms/LoopVectorize/AArch64/clmul.ll
new file mode 100644
index 0000000000000..d49b6b8885283
--- /dev/null
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/clmul.ll
@@ -0,0 +1,50 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
+; RUN: opt -passes=loop-vectorize -mtriple=aarch64 -mattr=+crypto -S %s | FileCheck %s
+
+declare i64 @llvm.clmul.i64(i64 %a, i64 %b)
+
+define void @clmul_loop(ptr %a, ptr %b, ptr %c, i64 %n) {
+; CHECK-LABEL: define void @clmul_loop(
+; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]], ptr [[C:%.*]], i64 [[N:%.*]]) #[[ATTR1:[0-9]+]] {
+; CHECK-NEXT: [[ENTRY:.*]]:
+; CHECK-NEXT: br label %[[FOR_BODY:.*]]
+; CHECK: [[FOR_BODY]]:
+; CHECK-NEXT: [[I:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[I_NEXT:%.*]], %[[FOR_BODY]] ]
+; CHECK-NEXT: [[PA:%.*]] = getelementptr i64, ptr [[A]], i64 [[I]]
+; CHECK-NEXT: [[PB:%.*]] = getelementptr i64, ptr [[B]], i64 [[I]]
+; CHECK-NEXT: [[PC:%.*]] = getelementptr i64, ptr [[C]], i64 [[I]]
+; CHECK-NEXT: [[VA:%.*]] = load i64, ptr [[PA]], align 8
+; CHECK-NEXT: [[VB:%.*]] = load i64, ptr [[PB]], align 8
+; CHECK-NEXT: [[R:%.*]] = call i64 @llvm.clmul.i64(i64 [[VA]], i64 [[VB]])
+; CHECK-NEXT: store i64 [[R]], ptr [[PC]], align 8
+; CHECK-NEXT: [[I_NEXT]] = add i64 [[I]], 1
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i64 [[I_NEXT]], [[N]]
+; CHECK-NEXT: br i1 [[CMP]], label %[[FOR_EXIT:.*]], label %[[FOR_BODY]]
+; CHECK: [[FOR_EXIT]]:
+; CHECK-NEXT: ret void
+;
+entry:
+ br label %for.body
+
+for.body:
+ %i = phi i64 [0, %entry], [%i.next, %for.body]
+
+ %pa = getelementptr i64, ptr %a, i64 %i
+ %pb = getelementptr i64, ptr %b, i64 %i
+ %pc = getelementptr i64, ptr %c, i64 %i
+
+ %va = load i64, ptr %pa
+ %vb = load i64, ptr %pb
+
+ %r = call i64 @llvm.clmul.i64(i64 %va, i64 %vb)
+
+ store i64 %r, ptr %pc
+
+ %i.next = add i64 %i, 1
+ %cmp = icmp eq i64 %i.next, %n
+ br i1 %cmp, label %for.exit, label %for.body
+
+for.exit:
+ ret void
+
+}
diff --git a/llvm/test/Transforms/LoopVectorize/RISCV/clmul.ll b/llvm/test/Transforms/LoopVectorize/RISCV/clmul.ll
new file mode 100644
index 0000000000000..e6e5b571729b0
--- /dev/null
+++ b/llvm/test/Transforms/LoopVectorize/RISCV/clmul.ll
@@ -0,0 +1,50 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
+; RUN: opt -passes=loop-vectorize -mtriple=riscv64 -mattr=+v -S %s | FileCheck %s
+
+declare i64 @llvm.clmul.i64(i64 %a, i64 %b)
+
+define void @clmul_loop(ptr %a, ptr %b, ptr %c, i64 %n) {
+; CHECK-LABEL: define void @clmul_loop(
+; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]], ptr [[C:%.*]], i64 [[N:%.*]]) #[[ATTR1:[0-9]+]] {
+; CHECK-NEXT: [[ENTRY:.*]]:
+; CHECK-NEXT: br label %[[FOR_BODY:.*]]
+; CHECK: [[FOR_BODY]]:
+; CHECK-NEXT: [[I:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[I_NEXT:%.*]], %[[FOR_BODY]] ]
+; CHECK-NEXT: [[PA:%.*]] = getelementptr i64, ptr [[A]], i64 [[I]]
+; CHECK-NEXT: [[PB:%.*]] = getelementptr i64, ptr [[B]], i64 [[I]]
+; CHECK-NEXT: [[PC:%.*]] = getelementptr i64, ptr [[C]], i64 [[I]]
+; CHECK-NEXT: [[VA:%.*]] = load i64, ptr [[PA]], align 8
+; CHECK-NEXT: [[VB:%.*]] = load i64, ptr [[PB]], align 8
+; CHECK-NEXT: [[R:%.*]] = call i64 @llvm.clmul.i64(i64 [[VA]], i64 [[VB]])
+; CHECK-NEXT: store i64 [[R]], ptr [[PC]], align 8
+; CHECK-NEXT: [[I_NEXT]] = add i64 [[I]], 1
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i64 [[I_NEXT]], [[N]]
+; CHECK-NEXT: br i1 [[CMP]], label %[[FOR_EXIT:.*]], label %[[FOR_BODY]]
+; CHECK: [[FOR_EXIT]]:
+; CHECK-NEXT: ret void
+;
+entry:
+ br label %for.body
+
+for.body:
+ %i = phi i64 [0, %entry], [%i.next, %for.body]
+
+ %pa = getelementptr i64, ptr %a, i64 %i
+ %pb = getelementptr i64, ptr %b, i64 %i
+ %pc = getelementptr i64, ptr %c, i64 %i
+
+ %va = load i64, ptr %pa
+ %vb = load i64, ptr %pb
+
+ %r = call i64 @llvm.clmul.i64(i64 %va, i64 %vb)
+
+ store i64 %r, ptr %pc
+
+ %i.next = add i64 %i, 1
+ %cmp = icmp eq i64 %i.next, %n
+ br i1 %cmp, label %for.exit, label %for.body
+
+for.exit:
+ ret void
+
+}
diff --git a/llvm/test/Transforms/LoopVectorize/X86/clmul.ll b/llvm/test/Transforms/LoopVectorize/X86/clmul.ll
new file mode 100644
index 0000000000000..897c3b9935ea5
--- /dev/null
+++ b/llvm/test/Transforms/LoopVectorize/X86/clmul.ll
@@ -0,0 +1,96 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
+; RUN: opt -passes=loop-vectorize -mtriple=x86_64 -mattr=+pclmul -S %s | FileCheck %s
+
+declare i64 @llvm.clmul.i64(i64 %a, i64 %b)
+
+define void @clmul_loop(ptr %a, ptr %b, ptr %c, i64 %n) {
+; CHECK-LABEL: define void @clmul_loop(
+; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]], ptr [[C:%.*]], i64 [[N:%.*]]) #[[ATTR1:[0-9]+]] {
+; CHECK-NEXT: [[ENTRY:.*]]:
+; CHECK-NEXT: [[B3:%.*]] = ptrtoint ptr [[B]] to i64
+; CHECK-NEXT: [[A2:%.*]] = ptrtoint ptr [[A]] to i64
+; CHECK-NEXT: [[C1:%.*]] = ptrtoint ptr [[C]] to i64
+; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 8
+; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_MEMCHECK:.*]]
+; CHECK: [[VECTOR_MEMCHECK]]:
+; CHECK-NEXT: [[TMP0:%.*]] = sub i64 [[C1]], [[A2]]
+; CHECK-NEXT: [[DIFF_CHECK:%.*]] = icmp ult i64 [[TMP0]], 32
+; CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[C1]], [[B3]]
+; CHECK-NEXT: [[DIFF_CHECK4:%.*]] = icmp ult i64 [[TMP1]], 32
+; CHECK-NEXT: [[CONFLICT_RDX:%.*]] = or i1 [[DIFF_CHECK]], [[DIFF_CHECK4]]
+; CHECK-NEXT: br i1 [[CONFLICT_RDX]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]
+; CHECK: [[VECTOR_PH]]:
+; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], 4
+; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]]
+; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK: [[VECTOR_BODY]]:
+; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i64, ptr [[A]], i64 [[INDEX]]
+; CHECK-NEXT: [[TMP3:%.*]] = getelementptr i64, ptr [[B]], i64 [[INDEX]]
+; CHECK-NEXT: [[TMP4:%.*]] = getelementptr i64, ptr [[C]], i64 [[INDEX]]
+; CHECK-NEXT: [[TMP5:%.*]] = getelementptr i64, ptr [[TMP2]], i64 2
+; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <2 x i64>, ptr [[TMP2]], align 8
+; CHECK-NEXT: [[WIDE_LOAD5:%.*]] = load <2 x i64>, ptr [[TMP5]], align 8
+; CHECK-NEXT: [[TMP6:%.*]] = getelementptr i64, ptr [[TMP3]], i64 2
+; CHECK-NEXT: [[WIDE_LOAD6:%.*]] = load <2 x i64>, ptr [[TMP3]], align 8
+; CHECK-NEXT: [[WIDE_LOAD7:%.*]] = load <2 x i64>, ptr [[TMP6]], align 8
+; CHECK-NEXT: [[TMP7:%.*]] = call <2 x i64> @llvm.clmul.v2i64(<2 x i64> [[WIDE_LOAD]], <2 x i64> [[WIDE_LOAD6]])
+; CHECK-NEXT: [[TMP8:%.*]] = call <2 x i64> @llvm.clmul.v2i64(<2 x i64> [[WIDE_LOAD5]], <2 x i64> [[WIDE_LOAD7]])
+; CHECK-NEXT: [[TMP9:%.*]] = getelementptr i64, ptr [[TMP4]], i64 2
+; CHECK-NEXT: store <2 x i64> [[TMP7]], ptr [[TMP4]], align 8
+; CHECK-NEXT: store <2 x i64> [[TMP8]], ptr [[TMP9]], align 8
+; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
+; CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
+; CHECK-NEXT: br i1 [[TMP10]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
+; CHECK: [[MIDDLE_BLOCK]]:
+; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]]
+; CHECK-NEXT: br i1 [[CMP_N]], label %[[FOR_EXIT:.*]], label %[[SCALAR_PH]]
+; CHECK: [[SCALAR_PH]]:
+; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_MEMCHECK]] ]
+; CHECK-NEXT: br label %[[FOR_BODY:.*]]
+; CHECK: [[FOR_BODY]]:
+; CHECK-NEXT: [[I:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[I_NEXT:%.*]], %[[FOR_BODY]] ]
+; CHECK-NEXT: [[PA:%.*]] = getelementptr i64, ptr [[A]], i64 [[I]]
+; CHECK-NEXT: [[PB:%.*]] = getelementptr i64, ptr [[B]], i64 [[I]]
+; CHECK-NEXT: [[PC:%.*]] = getelementptr i64, ptr [[C]], i64 [[I]]
+; CHECK-NEXT: [[VA:%.*]] = load i64, ptr [[PA]], align 8
+; CHECK-NEXT: [[VB:%.*]] = load i64, ptr [[PB]], align 8
+; CHECK-NEXT: [[R:%.*]] = call i64 @llvm.clmul.i64(i64 [[VA]], i64 [[VB]])
+; CHECK-NEXT: store i64 [[R]], ptr [[PC]], align 8
+; CHECK-NEXT: [[I_NEXT]] = add i64 [[I]], 1
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i64 [[I_NEXT]], [[N]]
+; CHECK-NEXT: br i1 [[CMP]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]
+; CHECK: [[FOR_EXIT]]:
+; CHECK-NEXT: ret void
+;
+entry:
+ br label %for.body
+
+for.body:
+ %i = phi i64 [0, %entry], [%i.next, %for.body]
+
+ %pa = getelementptr i64, ptr %a, i64 %i
+ %pb = getelementptr i64, ptr %b, i64 %i
+ %pc = getelementptr i64, ptr %c, i64 %i
+
+ %va = load i64, ptr %pa
+ %vb = load i64, ptr %pb
+
+ %r = call i64 @llvm.clmul.i64(i64 %va, i64 %vb)
+
+ store i64 %r, ptr %pc
+
+ %i.next = add i64 %i, 1
+ %cmp = icmp eq i64 %i.next, %n
+ br i1 %cmp, label %for.exit, label %for.body
+
+for.exit:
+ ret void
+
+}
+;.
+; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}
+; CHECK: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}
+; CHECK: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}
+; CHECK: [[LOOP3]] = distinct !{[[LOOP3]], [[META1]]}
+;.
diff --git a/llvm/test/Transforms/LoopVectorize/clmul.ll b/llvm/test/Transforms/LoopVectorize/clmul.ll
deleted file mode 100644
index c0102ba5a4034..0000000000000
--- a/llvm/test/Transforms/LoopVectorize/clmul.ll
+++ /dev/null
@@ -1,136 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
-; RUN: opt -passes=loop-vectorize -mtriple=x86_64 -mattr=+pclmul -S %s | FileCheck %s --check-prefix=X86
-; RUN: opt -passes=loop-vectorize -mtriple=aarch64 -mattr=+crypto -S %s | FileCheck %s --check-prefix=ARM
-; RUN: opt -passes=loop-vectorize -mtriple=riscv64 -mattr=+v -S %s | FileCheck %s --check-prefix=RISCV
-
-declare i64 @llvm.clmul.i64(i64 %a, i64 %b)
-
-define void @clmul_loop(ptr %a, ptr %b, ptr %c, i64 %n) {
-; X86-LABEL: define void @clmul_loop(
-; X86-SAME: ptr [[A:%.*]], ptr [[B:%.*]], ptr [[C:%.*]], i64 [[N:%.*]]) #[[ATTR1:[0-9]+]] {
-; X86-NEXT: [[ENTRY:.*]]:
-; X86-NEXT: [[B3:%.*]] = ptrtoint ptr [[B]] to i64
-; X86-NEXT: [[A2:%.*]] = ptrtoint ptr [[A]] to i64
-; X86-NEXT: [[C1:%.*]] = ptrtoint ptr [[C]] to i64
-; X86-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 8
-; X86-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_MEMCHECK:.*]]
-; X86: [[VECTOR_MEMCHECK]]:
-; X86-NEXT: [[TMP0:%.*]] = sub i64 [[C1]], [[A2]]
-; X86-NEXT: [[DIFF_CHECK:%.*]] = icmp ult i64 [[TMP0]], 32
-; X86-NEXT: [[TMP1:%.*]] = sub i64 [[C1]], [[B3]]
-; X86-NEXT: [[DIFF_CHECK4:%.*]] = icmp ult i64 [[TMP1]], 32
-; X86-NEXT: [[CONFLICT_RDX:%.*]] = or i1 [[DIFF_CHECK]], [[DIFF_CHECK4]]
-; X86-NEXT: br i1 [[CONFLICT_RDX]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]
-; X86: [[VECTOR_PH]]:
-; X86-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], 4
-; X86-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]]
-; X86-NEXT: br label %[[VECTOR_BODY:.*]]
-; X86: [[VECTOR_BODY]]:
-; X86-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
-; X86-NEXT: [[TMP2:%.*]] = getelementptr i64, ptr [[A]], i64 [[INDEX]]
-; X86-NEXT: [[TMP3:%.*]] = getelementptr i64, ptr [[B]], i64 [[INDEX]]
-; X86-NEXT: [[TMP4:%.*]] = getelementptr i64, ptr [[C]], i64 [[INDEX]]
-; X86-NEXT: [[TMP5:%.*]] = getelementptr i64, ptr [[TMP2]], i64 2
-; X86-NEXT: [[WIDE_LOAD:%.*]] = load <2 x i64>, ptr [[TMP2]], align 8
-; X86-NEXT: [[WIDE_LOAD5:%.*]] = load <2 x i64>, ptr [[TMP5]], align 8
-; X86-NEXT: [[TMP6:%.*]] = getelementptr i64, ptr [[TMP3]], i64 2
-; X86-NEXT: [[WIDE_LOAD6:%.*]] = load <2 x i64>, ptr [[TMP3]], align 8
-; X86-NEXT: [[WIDE_LOAD7:%.*]] = load <2 x i64>, ptr [[TMP6]], align 8
-; X86-NEXT: [[TMP7:%.*]] = call <2 x i64> @llvm.clmul.v2i64(<2 x i64> [[WIDE_LOAD]], <2 x i64> [[WIDE_LOAD6]])
-; X86-NEXT: [[TMP8:%.*]] = call <2 x i64> @llvm.clmul.v2i64(<2 x i64> [[WIDE_LOAD5]], <2 x i64> [[WIDE_LOAD7]])
-; X86-NEXT: [[TMP9:%.*]] = getelementptr i64, ptr [[TMP4]], i64 2
-; X86-NEXT: store <2 x i64> [[TMP7]], ptr [[TMP4]], align 8
-; X86-NEXT: store <2 x i64> [[TMP8]], ptr [[TMP9]], align 8
-; X86-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
-; X86-NEXT: [[TMP10:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
-; X86-NEXT: br i1 [[TMP10]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
-; X86: [[MIDDLE_BLOCK]]:
-; X86-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]]
-; X86-NEXT: br i1 [[CMP_N]], label %[[FOR_EXIT:.*]], label %[[SCALAR_PH]]
-; X86: [[SCALAR_PH]]:
-; X86-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_MEMCHECK]] ]
-; X86-NEXT: br label %[[FOR_BODY:.*]]
-; X86: [[FOR_BODY]]:
-; X86-NEXT: [[I:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[I_NEXT:%.*]], %[[FOR_BODY]] ]
-; X86-NEXT: [[PA:%.*]] = getelementptr i64, ptr [[A]], i64 [[I]]
-; X86-NEXT: [[PB:%.*]] = getelementptr i64, ptr [[B]], i64 [[I]]
-; X86-NEXT: [[PC:%.*]] = getelementptr i64, ptr [[C]], i64 [[I]]
-; X86-NEXT: [[VA:%.*]] = load i64, ptr [[PA]], align 8
-; X86-NEXT: [[VB:%.*]] = load i64, ptr [[PB]], align 8
-; X86-NEXT: [[R:%.*]] = call i64 @llvm.clmul.i64(i64 [[VA]], i64 [[VB]])
-; X86-NEXT: store i64 [[R]], ptr [[PC]], align 8
-; X86-NEXT: [[I_NEXT]] = add i64 [[I]], 1
-; X86-NEXT: [[CMP:%.*]] = icmp eq i64 [[I_NEXT]], [[N]]
-; X86-NEXT: br i1 [[CMP]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]
-; X86: [[FOR_EXIT]]:
-; X86-NEXT: ret void
-;
-; ARM-LABEL: define void @clmul_loop(
-; ARM-SAME: ptr [[A:%.*]], ptr [[B:%.*]], ptr [[C:%.*]], i64 [[N:%.*]]) #[[ATTR1:[0-9]+]] {
-; ARM-NEXT: [[ENTRY:.*]]:
-; ARM-NEXT: br label %[[FOR_BODY:.*]]
-; ARM: [[FOR_BODY]]:
-; ARM-NEXT: [[I:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[I_NEXT:%.*]], %[[FOR_BODY]] ]
-; ARM-NEXT: [[PA:%.*]] = getelementptr i64, ptr [[A]], i64 [[I]]
-; ARM-NEXT: [[PB:%.*]] = getelementptr i64, ptr [[B]], i64 [[I]]
-; ARM-NEXT: [[PC:%.*]] = getelementptr i64, ptr [[C]], i64 [[I]]
-; ARM-NEXT: [[VA:%.*]] = load i64, ptr [[PA]], align 8
-; ARM-NEXT: [[VB:%.*]] = load i64, ptr [[PB]], align 8
-; ARM-NEXT: [[R:%.*]] = call i64 @llvm.clmul.i64(i64 [[VA]], i64 [[VB]])
-; ARM-NEXT: store i64 [[R]], ptr [[PC]], align 8
-; ARM-NEXT: [[I_NEXT]] = add i64 [[I]], 1
-; ARM-NEXT: [[CMP:%.*]] = icmp eq i64 [[I_NEXT]], [[N]]
-; ARM-NEXT: br i1 [[CMP]], label %[[FOR_EXIT:.*]], label %[[FOR_BODY]]
-; ARM: [[FOR_EXIT]]:
-; ARM-NEXT: ret void
-;
-; RISCV-LABEL: define void @clmul_loop(
-; RISCV-SAME: ptr [[A:%.*]], ptr [[B:%.*]], ptr [[C:%.*]], i64 [[N:%.*]]) #[[ATTR1:[0-9]+]] {
-; RISCV-NEXT: [[ENTRY:.*]]:
-; RISCV-NEXT: br label %[[FOR_BODY:.*]]
-; RISCV: [[FOR_BODY]]:
-; RISCV-NEXT: [[I:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[I_NEXT:%.*]], %[[FOR_BODY]] ]
-; RISCV-NEXT: [[PA:%.*]] = getelementptr i64, ptr [[A]], i64 [[I]]
-; RISCV-NEXT: [[PB:%.*]] = getelementptr i64, ptr [[B]], i64 [[I]]
-; RISCV-NEXT: [[PC:%.*]] = getelementptr i64, ptr [[C]], i64 [[I]]
-; RISCV-NEXT: [[VA:%.*]] = load i64, ptr [[PA]], align 8
-; RISCV-NEXT: [[VB:%.*]] = load i64, ptr [[PB]], align 8
-; RISCV-NEXT: [[R:%.*]] = call i64 @llvm.clmul.i64(i64 [[VA]], i64 [[VB]])
-; RISCV-NEXT: store i64 [[R]], ptr [[PC]], align 8
-; RISCV-NEXT: [[I_NEXT]] = add i64 [[I]], 1
-; RISCV-NEXT: [[CMP:%.*]] = icmp eq i64 [[I_NEXT]], [[N]]
-; RISCV-NEXT: br i1 [[CMP]], label %[[FOR_EXIT:.*]], label %[[FOR_BODY]]
-; RISCV: [[FOR_EXIT]]:
-; RISCV-NEXT: ret void
-;
-entry:
- br label %for.body
-
-for.body:
- %i = phi i64 [0, %entry], [%i.next, %for.body]
-
- %pa = getelementptr i64, ptr %a, i64 %i
- %pb = getelementptr i64, ptr %b, i64 %i
- %pc = getelementptr i64, ptr %c, i64 %i
-
- %va = load i64, ptr %pa
- %vb = load i64, ptr %pb
-
- %r = call i64 @llvm.clmul.i64(i64 %va, i64 %vb)
-
- store i64 %r, ptr %pc
-
- %i.next = add i64 %i, 1
- %cmp = icmp eq i64 %i.next, %n
- br i1 %cmp, label %for.exit, label %for.body
-
-for.exit:
- ret void
-
-}
-;.
-; X86: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}
-; X86: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}
-; X86: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}
-; X86: [[LOOP3]] = distinct !{[[LOOP3]], [[META1]]}
-;.
>From dde8aa1904107ddf916df9a379dccc876289db1a Mon Sep 17 00:00:00 2001
From: pranshoe <pranshu.goyal71 at gmail.com>
Date: Fri, 6 Feb 2026 20:38:15 +0000
Subject: [PATCH 3/8] Make Intrinsic::clmul LoopVectorize tests vectorizable
for RISCV/ARM64
---
.../Transforms/LoopVectorize/AArch64/clmul.ll | 61 ++++++++++++++++---
.../Transforms/LoopVectorize/RISCV/clmul.ll | 58 +++++++++++++++---
2 files changed, 104 insertions(+), 15 deletions(-)
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/clmul.ll b/llvm/test/Transforms/LoopVectorize/AArch64/clmul.ll
index d49b6b8885283..46df643b2f2d2 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/clmul.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/clmul.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
-; RUN: opt -passes=loop-vectorize -mtriple=aarch64 -mattr=+crypto -S %s | FileCheck %s
+; RUN: opt -passes=loop-vectorize -mtriple=aarch64 -mattr=+crypto,+sve -scalable-vectorization=on -force-vector-width=2 -S %s | FileCheck %s
declare i64 @llvm.clmul.i64(i64 %a, i64 %b)
@@ -7,19 +7,60 @@ define void @clmul_loop(ptr %a, ptr %b, ptr %c, i64 %n) {
; CHECK-LABEL: define void @clmul_loop(
; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]], ptr [[C:%.*]], i64 [[N:%.*]]) #[[ATTR1:[0-9]+]] {
; CHECK-NEXT: [[ENTRY:.*]]:
+; CHECK-NEXT: [[B3:%.*]] = ptrtoint ptr [[B]] to i64
+; CHECK-NEXT: [[A2:%.*]] = ptrtoint ptr [[A]] to i64
+; CHECK-NEXT: [[C1:%.*]] = ptrtoint ptr [[C]] to i64
+; CHECK-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP1:%.*]] = shl nuw i64 [[TMP0]], 1
+; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], [[TMP1]]
+; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_MEMCHECK:.*]]
+; CHECK: [[VECTOR_MEMCHECK]]:
+; CHECK-NEXT: [[TMP2:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP3:%.*]] = mul nuw i64 [[TMP2]], 2
+; CHECK-NEXT: [[TMP4:%.*]] = mul i64 [[TMP3]], 8
+; CHECK-NEXT: [[TMP5:%.*]] = sub i64 [[C1]], [[A2]]
+; CHECK-NEXT: [[DIFF_CHECK:%.*]] = icmp ult i64 [[TMP5]], [[TMP4]]
+; CHECK-NEXT: [[TMP6:%.*]] = mul i64 [[TMP3]], 8
+; CHECK-NEXT: [[TMP7:%.*]] = sub i64 [[C1]], [[B3]]
+; CHECK-NEXT: [[DIFF_CHECK4:%.*]] = icmp ult i64 [[TMP7]], [[TMP6]]
+; CHECK-NEXT: [[CONFLICT_RDX:%.*]] = or i1 [[DIFF_CHECK]], [[DIFF_CHECK4]]
+; CHECK-NEXT: br i1 [[CONFLICT_RDX]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]
+; CHECK: [[VECTOR_PH]]:
+; CHECK-NEXT: [[TMP8:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP9:%.*]] = shl nuw i64 [[TMP8]], 1
+; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], [[TMP9]]
+; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]]
; CHECK-NEXT: br label %[[FOR_BODY:.*]]
; CHECK: [[FOR_BODY]]:
-; CHECK-NEXT: [[I:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[I_NEXT:%.*]], %[[FOR_BODY]] ]
+; CHECK-NEXT: [[I:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[FOR_BODY]] ]
; CHECK-NEXT: [[PA:%.*]] = getelementptr i64, ptr [[A]], i64 [[I]]
; CHECK-NEXT: [[PB:%.*]] = getelementptr i64, ptr [[B]], i64 [[I]]
; CHECK-NEXT: [[PC:%.*]] = getelementptr i64, ptr [[C]], i64 [[I]]
-; CHECK-NEXT: [[VA:%.*]] = load i64, ptr [[PA]], align 8
-; CHECK-NEXT: [[VB:%.*]] = load i64, ptr [[PB]], align 8
+; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 2 x i64>, ptr [[PA]], align 8
+; CHECK-NEXT: [[WIDE_LOAD5:%.*]] = load <vscale x 2 x i64>, ptr [[PB]], align 8
+; CHECK-NEXT: [[TMP13:%.*]] = call <vscale x 2 x i64> @llvm.clmul.nxv2i64(<vscale x 2 x i64> [[WIDE_LOAD]], <vscale x 2 x i64> [[WIDE_LOAD5]])
+; CHECK-NEXT: store <vscale x 2 x i64> [[TMP13]], ptr [[PC]], align 8
+; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[I]], [[TMP9]]
+; CHECK-NEXT: [[TMP14:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
+; CHECK-NEXT: br i1 [[TMP14]], label %[[MIDDLE_BLOCK:.*]], label %[[FOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
+; CHECK: [[MIDDLE_BLOCK]]:
+; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]]
+; CHECK-NEXT: br i1 [[CMP_N]], label %[[FOR_EXIT:.*]], label %[[SCALAR_PH]]
+; CHECK: [[SCALAR_PH]]:
+; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_MEMCHECK]] ]
+; CHECK-NEXT: br label %[[FOR_BODY1:.*]]
+; CHECK: [[FOR_BODY1]]:
+; CHECK-NEXT: [[I1:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[I_NEXT:%.*]], %[[FOR_BODY1]] ]
+; CHECK-NEXT: [[PA1:%.*]] = getelementptr i64, ptr [[A]], i64 [[I1]]
+; CHECK-NEXT: [[PB1:%.*]] = getelementptr i64, ptr [[B]], i64 [[I1]]
+; CHECK-NEXT: [[PC1:%.*]] = getelementptr i64, ptr [[C]], i64 [[I1]]
+; CHECK-NEXT: [[VA:%.*]] = load i64, ptr [[PA1]], align 8
+; CHECK-NEXT: [[VB:%.*]] = load i64, ptr [[PB1]], align 8
; CHECK-NEXT: [[R:%.*]] = call i64 @llvm.clmul.i64(i64 [[VA]], i64 [[VB]])
-; CHECK-NEXT: store i64 [[R]], ptr [[PC]], align 8
-; CHECK-NEXT: [[I_NEXT]] = add i64 [[I]], 1
+; CHECK-NEXT: store i64 [[R]], ptr [[PC1]], align 8
+; CHECK-NEXT: [[I_NEXT]] = add i64 [[I1]], 1
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i64 [[I_NEXT]], [[N]]
-; CHECK-NEXT: br i1 [[CMP]], label %[[FOR_EXIT:.*]], label %[[FOR_BODY]]
+; CHECK-NEXT: br i1 [[CMP]], label %[[FOR_EXIT]], label %[[FOR_BODY1]], !llvm.loop [[LOOP3:![0-9]+]]
; CHECK: [[FOR_EXIT]]:
; CHECK-NEXT: ret void
;
@@ -48,3 +89,9 @@ for.exit:
ret void
}
+;.
+; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}
+; CHECK: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}
+; CHECK: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}
+; CHECK: [[LOOP3]] = distinct !{[[LOOP3]], [[META1]]}
+;.
diff --git a/llvm/test/Transforms/LoopVectorize/RISCV/clmul.ll b/llvm/test/Transforms/LoopVectorize/RISCV/clmul.ll
index e6e5b571729b0..651adb67fcd85 100644
--- a/llvm/test/Transforms/LoopVectorize/RISCV/clmul.ll
+++ b/llvm/test/Transforms/LoopVectorize/RISCV/clmul.ll
@@ -1,25 +1,61 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
-; RUN: opt -passes=loop-vectorize -mtriple=riscv64 -mattr=+v -S %s | FileCheck %s
+; RUN: opt -passes=loop-vectorize -mtriple=riscv64 -scalable-vectorization=on -force-vector-width=2 -mattr=+v -S %s | FileCheck %s
declare i64 @llvm.clmul.i64(i64 %a, i64 %b)
define void @clmul_loop(ptr %a, ptr %b, ptr %c, i64 %n) {
; CHECK-LABEL: define void @clmul_loop(
; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]], ptr [[C:%.*]], i64 [[N:%.*]]) #[[ATTR1:[0-9]+]] {
-; CHECK-NEXT: [[ENTRY:.*]]:
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[B3:%.*]] = ptrtoint ptr [[B]] to i64
+; CHECK-NEXT: [[A2:%.*]] = ptrtoint ptr [[A]] to i64
+; CHECK-NEXT: [[C1:%.*]] = ptrtoint ptr [[C]] to i64
; CHECK-NEXT: br label %[[FOR_BODY:.*]]
; CHECK: [[FOR_BODY]]:
-; CHECK-NEXT: [[I:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[I_NEXT:%.*]], %[[FOR_BODY]] ]
+; CHECK-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP1:%.*]] = mul nuw i64 [[TMP0]], 2
+; CHECK-NEXT: [[TMP2:%.*]] = mul i64 [[TMP1]], 8
+; CHECK-NEXT: [[TMP3:%.*]] = sub i64 [[C1]], [[A2]]
+; CHECK-NEXT: [[DIFF_CHECK:%.*]] = icmp ult i64 [[TMP3]], [[TMP2]]
+; CHECK-NEXT: [[TMP4:%.*]] = mul i64 [[TMP1]], 8
+; CHECK-NEXT: [[TMP5:%.*]] = sub i64 [[C1]], [[B3]]
+; CHECK-NEXT: [[DIFF_CHECK4:%.*]] = icmp ult i64 [[TMP5]], [[TMP4]]
+; CHECK-NEXT: [[CONFLICT_RDX:%.*]] = or i1 [[DIFF_CHECK]], [[DIFF_CHECK4]]
+; CHECK-NEXT: br i1 [[CONFLICT_RDX]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
+; CHECK: [[VECTOR_PH]]:
+; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK: [[VECTOR_BODY]]:
+; CHECK-NEXT: [[I:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_EVL_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[AVL:%.*]] = phi i64 [ [[N]], %[[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[TMP6:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 2, i1 true)
; CHECK-NEXT: [[PA:%.*]] = getelementptr i64, ptr [[A]], i64 [[I]]
; CHECK-NEXT: [[PB:%.*]] = getelementptr i64, ptr [[B]], i64 [[I]]
; CHECK-NEXT: [[PC:%.*]] = getelementptr i64, ptr [[C]], i64 [[I]]
-; CHECK-NEXT: [[VA:%.*]] = load i64, ptr [[PA]], align 8
-; CHECK-NEXT: [[VB:%.*]] = load i64, ptr [[PB]], align 8
+; CHECK-NEXT: [[VP_OP_LOAD:%.*]] = call <vscale x 2 x i64> @llvm.vp.load.nxv2i64.p0(ptr align 8 [[PA]], <vscale x 2 x i1> splat (i1 true), i32 [[TMP6]])
+; CHECK-NEXT: [[VP_OP_LOAD5:%.*]] = call <vscale x 2 x i64> @llvm.vp.load.nxv2i64.p0(ptr align 8 [[PB]], <vscale x 2 x i1> splat (i1 true), i32 [[TMP6]])
+; CHECK-NEXT: [[TMP10:%.*]] = call <vscale x 2 x i64> @llvm.clmul.nxv2i64(<vscale x 2 x i64> [[VP_OP_LOAD]], <vscale x 2 x i64> [[VP_OP_LOAD5]])
+; CHECK-NEXT: call void @llvm.vp.store.nxv2i64.p0(<vscale x 2 x i64> [[TMP10]], ptr align 8 [[PC]], <vscale x 2 x i1> splat (i1 true), i32 [[TMP6]])
+; CHECK-NEXT: [[TMP11:%.*]] = zext i32 [[TMP6]] to i64
+; CHECK-NEXT: [[INDEX_EVL_NEXT]] = add i64 [[TMP11]], [[I]]
+; CHECK-NEXT: [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP11]]
+; CHECK-NEXT: [[TMP12:%.*]] = icmp eq i64 [[AVL_NEXT]], 0
+; CHECK-NEXT: br i1 [[TMP12]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
+; CHECK: [[MIDDLE_BLOCK]]:
+; CHECK-NEXT: br label %[[FOR_EXIT:.*]]
+; CHECK: [[SCALAR_PH]]:
+; CHECK-NEXT: br label %[[FOR_BODY1:.*]]
+; CHECK: [[FOR_BODY1]]:
+; CHECK-NEXT: [[I1:%.*]] = phi i64 [ 0, %[[SCALAR_PH]] ], [ [[I_NEXT:%.*]], %[[FOR_BODY1]] ]
+; CHECK-NEXT: [[PA1:%.*]] = getelementptr i64, ptr [[A]], i64 [[I1]]
+; CHECK-NEXT: [[PB1:%.*]] = getelementptr i64, ptr [[B]], i64 [[I1]]
+; CHECK-NEXT: [[PC1:%.*]] = getelementptr i64, ptr [[C]], i64 [[I1]]
+; CHECK-NEXT: [[VA:%.*]] = load i64, ptr [[PA1]], align 8
+; CHECK-NEXT: [[VB:%.*]] = load i64, ptr [[PB1]], align 8
; CHECK-NEXT: [[R:%.*]] = call i64 @llvm.clmul.i64(i64 [[VA]], i64 [[VB]])
-; CHECK-NEXT: store i64 [[R]], ptr [[PC]], align 8
-; CHECK-NEXT: [[I_NEXT]] = add i64 [[I]], 1
+; CHECK-NEXT: store i64 [[R]], ptr [[PC1]], align 8
+; CHECK-NEXT: [[I_NEXT]] = add i64 [[I1]], 1
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i64 [[I_NEXT]], [[N]]
-; CHECK-NEXT: br i1 [[CMP]], label %[[FOR_EXIT:.*]], label %[[FOR_BODY]]
+; CHECK-NEXT: br i1 [[CMP]], label %[[FOR_EXIT]], label %[[FOR_BODY1]], !llvm.loop [[LOOP3:![0-9]+]]
; CHECK: [[FOR_EXIT]]:
; CHECK-NEXT: ret void
;
@@ -48,3 +84,9 @@ for.exit:
ret void
}
+;.
+; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}
+; CHECK: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}
+; CHECK: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}
+; CHECK: [[LOOP3]] = distinct !{[[LOOP3]], [[META1]]}
+;.
>From efbac1c856abc3ee6be08a7ca80f39f5ef0f1a6d Mon Sep 17 00:00:00 2001
From: pranshoe <pranshu.goyal71 at gmail.com>
Date: Tue, 10 Feb 2026 09:29:11 +0000
Subject: [PATCH 4/8] Revert "Make Intrinsic::clmul LoopVectorize tests
vectorizable for RISCV/ARM64"
This reverts commit b97a77395be842a5bef6916bd1a2d3f82a79e4e4.
---
.../Transforms/LoopVectorize/AArch64/clmul.ll | 61 +++----------------
.../Transforms/LoopVectorize/RISCV/clmul.ll | 58 +++---------------
2 files changed, 15 insertions(+), 104 deletions(-)
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/clmul.ll b/llvm/test/Transforms/LoopVectorize/AArch64/clmul.ll
index 46df643b2f2d2..d49b6b8885283 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/clmul.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/clmul.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
-; RUN: opt -passes=loop-vectorize -mtriple=aarch64 -mattr=+crypto,+sve -scalable-vectorization=on -force-vector-width=2 -S %s | FileCheck %s
+; RUN: opt -passes=loop-vectorize -mtriple=aarch64 -mattr=+crypto -S %s | FileCheck %s
declare i64 @llvm.clmul.i64(i64 %a, i64 %b)
@@ -7,60 +7,19 @@ define void @clmul_loop(ptr %a, ptr %b, ptr %c, i64 %n) {
; CHECK-LABEL: define void @clmul_loop(
; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]], ptr [[C:%.*]], i64 [[N:%.*]]) #[[ATTR1:[0-9]+]] {
; CHECK-NEXT: [[ENTRY:.*]]:
-; CHECK-NEXT: [[B3:%.*]] = ptrtoint ptr [[B]] to i64
-; CHECK-NEXT: [[A2:%.*]] = ptrtoint ptr [[A]] to i64
-; CHECK-NEXT: [[C1:%.*]] = ptrtoint ptr [[C]] to i64
-; CHECK-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64()
-; CHECK-NEXT: [[TMP1:%.*]] = shl nuw i64 [[TMP0]], 1
-; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], [[TMP1]]
-; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_MEMCHECK:.*]]
-; CHECK: [[VECTOR_MEMCHECK]]:
-; CHECK-NEXT: [[TMP2:%.*]] = call i64 @llvm.vscale.i64()
-; CHECK-NEXT: [[TMP3:%.*]] = mul nuw i64 [[TMP2]], 2
-; CHECK-NEXT: [[TMP4:%.*]] = mul i64 [[TMP3]], 8
-; CHECK-NEXT: [[TMP5:%.*]] = sub i64 [[C1]], [[A2]]
-; CHECK-NEXT: [[DIFF_CHECK:%.*]] = icmp ult i64 [[TMP5]], [[TMP4]]
-; CHECK-NEXT: [[TMP6:%.*]] = mul i64 [[TMP3]], 8
-; CHECK-NEXT: [[TMP7:%.*]] = sub i64 [[C1]], [[B3]]
-; CHECK-NEXT: [[DIFF_CHECK4:%.*]] = icmp ult i64 [[TMP7]], [[TMP6]]
-; CHECK-NEXT: [[CONFLICT_RDX:%.*]] = or i1 [[DIFF_CHECK]], [[DIFF_CHECK4]]
-; CHECK-NEXT: br i1 [[CONFLICT_RDX]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]
-; CHECK: [[VECTOR_PH]]:
-; CHECK-NEXT: [[TMP8:%.*]] = call i64 @llvm.vscale.i64()
-; CHECK-NEXT: [[TMP9:%.*]] = shl nuw i64 [[TMP8]], 1
-; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], [[TMP9]]
-; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]]
; CHECK-NEXT: br label %[[FOR_BODY:.*]]
; CHECK: [[FOR_BODY]]:
-; CHECK-NEXT: [[I:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[FOR_BODY]] ]
+; CHECK-NEXT: [[I:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[I_NEXT:%.*]], %[[FOR_BODY]] ]
; CHECK-NEXT: [[PA:%.*]] = getelementptr i64, ptr [[A]], i64 [[I]]
; CHECK-NEXT: [[PB:%.*]] = getelementptr i64, ptr [[B]], i64 [[I]]
; CHECK-NEXT: [[PC:%.*]] = getelementptr i64, ptr [[C]], i64 [[I]]
-; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 2 x i64>, ptr [[PA]], align 8
-; CHECK-NEXT: [[WIDE_LOAD5:%.*]] = load <vscale x 2 x i64>, ptr [[PB]], align 8
-; CHECK-NEXT: [[TMP13:%.*]] = call <vscale x 2 x i64> @llvm.clmul.nxv2i64(<vscale x 2 x i64> [[WIDE_LOAD]], <vscale x 2 x i64> [[WIDE_LOAD5]])
-; CHECK-NEXT: store <vscale x 2 x i64> [[TMP13]], ptr [[PC]], align 8
-; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[I]], [[TMP9]]
-; CHECK-NEXT: [[TMP14:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
-; CHECK-NEXT: br i1 [[TMP14]], label %[[MIDDLE_BLOCK:.*]], label %[[FOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
-; CHECK: [[MIDDLE_BLOCK]]:
-; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]]
-; CHECK-NEXT: br i1 [[CMP_N]], label %[[FOR_EXIT:.*]], label %[[SCALAR_PH]]
-; CHECK: [[SCALAR_PH]]:
-; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_MEMCHECK]] ]
-; CHECK-NEXT: br label %[[FOR_BODY1:.*]]
-; CHECK: [[FOR_BODY1]]:
-; CHECK-NEXT: [[I1:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[I_NEXT:%.*]], %[[FOR_BODY1]] ]
-; CHECK-NEXT: [[PA1:%.*]] = getelementptr i64, ptr [[A]], i64 [[I1]]
-; CHECK-NEXT: [[PB1:%.*]] = getelementptr i64, ptr [[B]], i64 [[I1]]
-; CHECK-NEXT: [[PC1:%.*]] = getelementptr i64, ptr [[C]], i64 [[I1]]
-; CHECK-NEXT: [[VA:%.*]] = load i64, ptr [[PA1]], align 8
-; CHECK-NEXT: [[VB:%.*]] = load i64, ptr [[PB1]], align 8
+; CHECK-NEXT: [[VA:%.*]] = load i64, ptr [[PA]], align 8
+; CHECK-NEXT: [[VB:%.*]] = load i64, ptr [[PB]], align 8
; CHECK-NEXT: [[R:%.*]] = call i64 @llvm.clmul.i64(i64 [[VA]], i64 [[VB]])
-; CHECK-NEXT: store i64 [[R]], ptr [[PC1]], align 8
-; CHECK-NEXT: [[I_NEXT]] = add i64 [[I1]], 1
+; CHECK-NEXT: store i64 [[R]], ptr [[PC]], align 8
+; CHECK-NEXT: [[I_NEXT]] = add i64 [[I]], 1
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i64 [[I_NEXT]], [[N]]
-; CHECK-NEXT: br i1 [[CMP]], label %[[FOR_EXIT]], label %[[FOR_BODY1]], !llvm.loop [[LOOP3:![0-9]+]]
+; CHECK-NEXT: br i1 [[CMP]], label %[[FOR_EXIT:.*]], label %[[FOR_BODY]]
; CHECK: [[FOR_EXIT]]:
; CHECK-NEXT: ret void
;
@@ -89,9 +48,3 @@ for.exit:
ret void
}
-;.
-; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}
-; CHECK: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}
-; CHECK: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}
-; CHECK: [[LOOP3]] = distinct !{[[LOOP3]], [[META1]]}
-;.
diff --git a/llvm/test/Transforms/LoopVectorize/RISCV/clmul.ll b/llvm/test/Transforms/LoopVectorize/RISCV/clmul.ll
index 651adb67fcd85..e6e5b571729b0 100644
--- a/llvm/test/Transforms/LoopVectorize/RISCV/clmul.ll
+++ b/llvm/test/Transforms/LoopVectorize/RISCV/clmul.ll
@@ -1,61 +1,25 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
-; RUN: opt -passes=loop-vectorize -mtriple=riscv64 -scalable-vectorization=on -force-vector-width=2 -mattr=+v -S %s | FileCheck %s
+; RUN: opt -passes=loop-vectorize -mtriple=riscv64 -mattr=+v -S %s | FileCheck %s
declare i64 @llvm.clmul.i64(i64 %a, i64 %b)
define void @clmul_loop(ptr %a, ptr %b, ptr %c, i64 %n) {
; CHECK-LABEL: define void @clmul_loop(
; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]], ptr [[C:%.*]], i64 [[N:%.*]]) #[[ATTR1:[0-9]+]] {
-; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: [[B3:%.*]] = ptrtoint ptr [[B]] to i64
-; CHECK-NEXT: [[A2:%.*]] = ptrtoint ptr [[A]] to i64
-; CHECK-NEXT: [[C1:%.*]] = ptrtoint ptr [[C]] to i64
+; CHECK-NEXT: [[ENTRY:.*]]:
; CHECK-NEXT: br label %[[FOR_BODY:.*]]
; CHECK: [[FOR_BODY]]:
-; CHECK-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64()
-; CHECK-NEXT: [[TMP1:%.*]] = mul nuw i64 [[TMP0]], 2
-; CHECK-NEXT: [[TMP2:%.*]] = mul i64 [[TMP1]], 8
-; CHECK-NEXT: [[TMP3:%.*]] = sub i64 [[C1]], [[A2]]
-; CHECK-NEXT: [[DIFF_CHECK:%.*]] = icmp ult i64 [[TMP3]], [[TMP2]]
-; CHECK-NEXT: [[TMP4:%.*]] = mul i64 [[TMP1]], 8
-; CHECK-NEXT: [[TMP5:%.*]] = sub i64 [[C1]], [[B3]]
-; CHECK-NEXT: [[DIFF_CHECK4:%.*]] = icmp ult i64 [[TMP5]], [[TMP4]]
-; CHECK-NEXT: [[CONFLICT_RDX:%.*]] = or i1 [[DIFF_CHECK]], [[DIFF_CHECK4]]
-; CHECK-NEXT: br i1 [[CONFLICT_RDX]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
-; CHECK: [[VECTOR_PH]]:
-; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
-; CHECK: [[VECTOR_BODY]]:
-; CHECK-NEXT: [[I:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_EVL_NEXT:%.*]], %[[VECTOR_BODY]] ]
-; CHECK-NEXT: [[AVL:%.*]] = phi i64 [ [[N]], %[[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], %[[VECTOR_BODY]] ]
-; CHECK-NEXT: [[TMP6:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 2, i1 true)
+; CHECK-NEXT: [[I:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[I_NEXT:%.*]], %[[FOR_BODY]] ]
; CHECK-NEXT: [[PA:%.*]] = getelementptr i64, ptr [[A]], i64 [[I]]
; CHECK-NEXT: [[PB:%.*]] = getelementptr i64, ptr [[B]], i64 [[I]]
; CHECK-NEXT: [[PC:%.*]] = getelementptr i64, ptr [[C]], i64 [[I]]
-; CHECK-NEXT: [[VP_OP_LOAD:%.*]] = call <vscale x 2 x i64> @llvm.vp.load.nxv2i64.p0(ptr align 8 [[PA]], <vscale x 2 x i1> splat (i1 true), i32 [[TMP6]])
-; CHECK-NEXT: [[VP_OP_LOAD5:%.*]] = call <vscale x 2 x i64> @llvm.vp.load.nxv2i64.p0(ptr align 8 [[PB]], <vscale x 2 x i1> splat (i1 true), i32 [[TMP6]])
-; CHECK-NEXT: [[TMP10:%.*]] = call <vscale x 2 x i64> @llvm.clmul.nxv2i64(<vscale x 2 x i64> [[VP_OP_LOAD]], <vscale x 2 x i64> [[VP_OP_LOAD5]])
-; CHECK-NEXT: call void @llvm.vp.store.nxv2i64.p0(<vscale x 2 x i64> [[TMP10]], ptr align 8 [[PC]], <vscale x 2 x i1> splat (i1 true), i32 [[TMP6]])
-; CHECK-NEXT: [[TMP11:%.*]] = zext i32 [[TMP6]] to i64
-; CHECK-NEXT: [[INDEX_EVL_NEXT]] = add i64 [[TMP11]], [[I]]
-; CHECK-NEXT: [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP11]]
-; CHECK-NEXT: [[TMP12:%.*]] = icmp eq i64 [[AVL_NEXT]], 0
-; CHECK-NEXT: br i1 [[TMP12]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
-; CHECK: [[MIDDLE_BLOCK]]:
-; CHECK-NEXT: br label %[[FOR_EXIT:.*]]
-; CHECK: [[SCALAR_PH]]:
-; CHECK-NEXT: br label %[[FOR_BODY1:.*]]
-; CHECK: [[FOR_BODY1]]:
-; CHECK-NEXT: [[I1:%.*]] = phi i64 [ 0, %[[SCALAR_PH]] ], [ [[I_NEXT:%.*]], %[[FOR_BODY1]] ]
-; CHECK-NEXT: [[PA1:%.*]] = getelementptr i64, ptr [[A]], i64 [[I1]]
-; CHECK-NEXT: [[PB1:%.*]] = getelementptr i64, ptr [[B]], i64 [[I1]]
-; CHECK-NEXT: [[PC1:%.*]] = getelementptr i64, ptr [[C]], i64 [[I1]]
-; CHECK-NEXT: [[VA:%.*]] = load i64, ptr [[PA1]], align 8
-; CHECK-NEXT: [[VB:%.*]] = load i64, ptr [[PB1]], align 8
+; CHECK-NEXT: [[VA:%.*]] = load i64, ptr [[PA]], align 8
+; CHECK-NEXT: [[VB:%.*]] = load i64, ptr [[PB]], align 8
; CHECK-NEXT: [[R:%.*]] = call i64 @llvm.clmul.i64(i64 [[VA]], i64 [[VB]])
-; CHECK-NEXT: store i64 [[R]], ptr [[PC1]], align 8
-; CHECK-NEXT: [[I_NEXT]] = add i64 [[I1]], 1
+; CHECK-NEXT: store i64 [[R]], ptr [[PC]], align 8
+; CHECK-NEXT: [[I_NEXT]] = add i64 [[I]], 1
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i64 [[I_NEXT]], [[N]]
-; CHECK-NEXT: br i1 [[CMP]], label %[[FOR_EXIT]], label %[[FOR_BODY1]], !llvm.loop [[LOOP3:![0-9]+]]
+; CHECK-NEXT: br i1 [[CMP]], label %[[FOR_EXIT:.*]], label %[[FOR_BODY]]
; CHECK: [[FOR_EXIT]]:
; CHECK-NEXT: ret void
;
@@ -84,9 +48,3 @@ for.exit:
ret void
}
-;.
-; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}
-; CHECK: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}
-; CHECK: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}
-; CHECK: [[LOOP3]] = distinct !{[[LOOP3]], [[META1]]}
-;.
>From ebd40a54f2183cdea687e608db98b5ea093e924d Mon Sep 17 00:00:00 2001
From: pranshoe <pranshu.goyal71 at gmail.com>
Date: Tue, 10 Feb 2026 09:33:41 +0000
Subject: [PATCH 5/8] Add tests for general support of Intrinsic::clmul
vectorization
---
.../Transforms/LoopVectorize/intrinsic.ll | 33 +++++++++++++++++++
1 file changed, 33 insertions(+)
diff --git a/llvm/test/Transforms/LoopVectorize/intrinsic.ll b/llvm/test/Transforms/LoopVectorize/intrinsic.ll
index 10d83a456d0e2..c46c71d65910d 100644
--- a/llvm/test/Transforms/LoopVectorize/intrinsic.ll
+++ b/llvm/test/Transforms/LoopVectorize/intrinsic.ll
@@ -1904,3 +1904,36 @@ for.body: ; preds = %entry, %for.body
exit: ; preds = %for.body, %entry
ret void
}
+
+declare i64 @llvm.clmul.i64(i64 %a, i64 %b)
+
+define void @clmul_i64(ptr %a, ptr %b, ptr %c, i64 %n) {
+; CHECK-LABEL: @clmul_i64(
+; CHECK: llvm.clmul.v4i64
+; CHECK: ret void
+;
+entry:
+ br label %for.body
+
+for.body: ; preds = %entry, %for.body
+ %i = phi i64 [0, %entry], [%i.next, %for.body]
+
+ %pa = getelementptr i64, ptr %a, i64 %i
+ %pb = getelementptr i64, ptr %b, i64 %i
+ %pc = getelementptr i64, ptr %c, i64 %i
+
+ %va = load i64, ptr %pa
+ %vb = load i64, ptr %pb
+
+ %r = call i64 @llvm.clmul.i64(i64 %va, i64 %vb)
+
+ store i64 %r, ptr %pc
+
+ %i.next = add i64 %i, 1
+ %cmp = icmp eq i64 %i.next, %n
+ br i1 %cmp, label %exit, label %for.body
+
+exit: ; preds = %for.body, %entry
+ ret void
+
+}
>From 6cec24397a8d7075a0b92d969709c2280d4f362a Mon Sep 17 00:00:00 2001
From: pranshoe <pranshu.goyal71 at gmail.com>
Date: Sat, 14 Feb 2026 16:57:41 +0000
Subject: [PATCH 6/8] Add a second run without pclmul for x86 tests of
Intrinsic::clmul
---
.../Transforms/LoopVectorize/X86/clmul.ll | 148 ++++++++++--------
1 file changed, 84 insertions(+), 64 deletions(-)
diff --git a/llvm/test/Transforms/LoopVectorize/X86/clmul.ll b/llvm/test/Transforms/LoopVectorize/X86/clmul.ll
index 897c3b9935ea5..20a154ef14152 100644
--- a/llvm/test/Transforms/LoopVectorize/X86/clmul.ll
+++ b/llvm/test/Transforms/LoopVectorize/X86/clmul.ll
@@ -1,67 +1,87 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
-; RUN: opt -passes=loop-vectorize -mtriple=x86_64 -mattr=+pclmul -S %s | FileCheck %s
+; RUN: opt -passes=loop-vectorize -mtriple=x86_64 -mattr=+pclmul -S %s | FileCheck %s --check-prefix=WITH-PCLMUL
+; RUN: opt -passes=loop-vectorize -mtriple=x86_64 -mattr=-pclmul -S %s | FileCheck %s --check-prefix=WITH-NO-PCLMUL
declare i64 @llvm.clmul.i64(i64 %a, i64 %b)
-define void @clmul_loop(ptr %a, ptr %b, ptr %c, i64 %n) {
-; CHECK-LABEL: define void @clmul_loop(
-; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]], ptr [[C:%.*]], i64 [[N:%.*]]) #[[ATTR1:[0-9]+]] {
-; CHECK-NEXT: [[ENTRY:.*]]:
-; CHECK-NEXT: [[B3:%.*]] = ptrtoint ptr [[B]] to i64
-; CHECK-NEXT: [[A2:%.*]] = ptrtoint ptr [[A]] to i64
-; CHECK-NEXT: [[C1:%.*]] = ptrtoint ptr [[C]] to i64
-; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 8
-; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_MEMCHECK:.*]]
-; CHECK: [[VECTOR_MEMCHECK]]:
-; CHECK-NEXT: [[TMP0:%.*]] = sub i64 [[C1]], [[A2]]
-; CHECK-NEXT: [[DIFF_CHECK:%.*]] = icmp ult i64 [[TMP0]], 32
-; CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[C1]], [[B3]]
-; CHECK-NEXT: [[DIFF_CHECK4:%.*]] = icmp ult i64 [[TMP1]], 32
-; CHECK-NEXT: [[CONFLICT_RDX:%.*]] = or i1 [[DIFF_CHECK]], [[DIFF_CHECK4]]
-; CHECK-NEXT: br i1 [[CONFLICT_RDX]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]
-; CHECK: [[VECTOR_PH]]:
-; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], 4
-; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]]
-; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
-; CHECK: [[VECTOR_BODY]]:
-; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
-; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i64, ptr [[A]], i64 [[INDEX]]
-; CHECK-NEXT: [[TMP3:%.*]] = getelementptr i64, ptr [[B]], i64 [[INDEX]]
-; CHECK-NEXT: [[TMP4:%.*]] = getelementptr i64, ptr [[C]], i64 [[INDEX]]
-; CHECK-NEXT: [[TMP5:%.*]] = getelementptr i64, ptr [[TMP2]], i64 2
-; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <2 x i64>, ptr [[TMP2]], align 8
-; CHECK-NEXT: [[WIDE_LOAD5:%.*]] = load <2 x i64>, ptr [[TMP5]], align 8
-; CHECK-NEXT: [[TMP6:%.*]] = getelementptr i64, ptr [[TMP3]], i64 2
-; CHECK-NEXT: [[WIDE_LOAD6:%.*]] = load <2 x i64>, ptr [[TMP3]], align 8
-; CHECK-NEXT: [[WIDE_LOAD7:%.*]] = load <2 x i64>, ptr [[TMP6]], align 8
-; CHECK-NEXT: [[TMP7:%.*]] = call <2 x i64> @llvm.clmul.v2i64(<2 x i64> [[WIDE_LOAD]], <2 x i64> [[WIDE_LOAD6]])
-; CHECK-NEXT: [[TMP8:%.*]] = call <2 x i64> @llvm.clmul.v2i64(<2 x i64> [[WIDE_LOAD5]], <2 x i64> [[WIDE_LOAD7]])
-; CHECK-NEXT: [[TMP9:%.*]] = getelementptr i64, ptr [[TMP4]], i64 2
-; CHECK-NEXT: store <2 x i64> [[TMP7]], ptr [[TMP4]], align 8
-; CHECK-NEXT: store <2 x i64> [[TMP8]], ptr [[TMP9]], align 8
-; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
-; CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
-; CHECK-NEXT: br i1 [[TMP10]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
-; CHECK: [[MIDDLE_BLOCK]]:
-; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]]
-; CHECK-NEXT: br i1 [[CMP_N]], label %[[FOR_EXIT:.*]], label %[[SCALAR_PH]]
-; CHECK: [[SCALAR_PH]]:
-; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_MEMCHECK]] ]
-; CHECK-NEXT: br label %[[FOR_BODY:.*]]
-; CHECK: [[FOR_BODY]]:
-; CHECK-NEXT: [[I:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[I_NEXT:%.*]], %[[FOR_BODY]] ]
-; CHECK-NEXT: [[PA:%.*]] = getelementptr i64, ptr [[A]], i64 [[I]]
-; CHECK-NEXT: [[PB:%.*]] = getelementptr i64, ptr [[B]], i64 [[I]]
-; CHECK-NEXT: [[PC:%.*]] = getelementptr i64, ptr [[C]], i64 [[I]]
-; CHECK-NEXT: [[VA:%.*]] = load i64, ptr [[PA]], align 8
-; CHECK-NEXT: [[VB:%.*]] = load i64, ptr [[PB]], align 8
-; CHECK-NEXT: [[R:%.*]] = call i64 @llvm.clmul.i64(i64 [[VA]], i64 [[VB]])
-; CHECK-NEXT: store i64 [[R]], ptr [[PC]], align 8
-; CHECK-NEXT: [[I_NEXT]] = add i64 [[I]], 1
-; CHECK-NEXT: [[CMP:%.*]] = icmp eq i64 [[I_NEXT]], [[N]]
-; CHECK-NEXT: br i1 [[CMP]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]
-; CHECK: [[FOR_EXIT]]:
-; CHECK-NEXT: ret void
+define void @clmul_loop(ptr %a, ptr %b, ptr %c, i64 %n){
+; WITH-PCLMUL-LABEL: define void @clmul_loop(
+; WITH-PCLMUL-SAME: ptr [[A:%.*]], ptr [[B:%.*]], ptr [[C:%.*]], i64 [[N:%.*]]) #[[ATTR1:[0-9]+]] {
+; WITH-PCLMUL-NEXT: [[ENTRY:.*]]:
+; WITH-PCLMUL-NEXT: [[B3:%.*]] = ptrtoint ptr [[B]] to i64
+; WITH-PCLMUL-NEXT: [[A2:%.*]] = ptrtoint ptr [[A]] to i64
+; WITH-PCLMUL-NEXT: [[C1:%.*]] = ptrtoint ptr [[C]] to i64
+; WITH-PCLMUL-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 8
+; WITH-PCLMUL-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_MEMCHECK:.*]]
+; WITH-PCLMUL: [[VECTOR_MEMCHECK]]:
+; WITH-PCLMUL-NEXT: [[TMP0:%.*]] = sub i64 [[C1]], [[A2]]
+; WITH-PCLMUL-NEXT: [[DIFF_CHECK:%.*]] = icmp ult i64 [[TMP0]], 32
+; WITH-PCLMUL-NEXT: [[TMP1:%.*]] = sub i64 [[C1]], [[B3]]
+; WITH-PCLMUL-NEXT: [[DIFF_CHECK4:%.*]] = icmp ult i64 [[TMP1]], 32
+; WITH-PCLMUL-NEXT: [[CONFLICT_RDX:%.*]] = or i1 [[DIFF_CHECK]], [[DIFF_CHECK4]]
+; WITH-PCLMUL-NEXT: br i1 [[CONFLICT_RDX]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]
+; WITH-PCLMUL: [[VECTOR_PH]]:
+; WITH-PCLMUL-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], 4
+; WITH-PCLMUL-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]]
+; WITH-PCLMUL-NEXT: br label %[[VECTOR_BODY:.*]]
+; WITH-PCLMUL: [[VECTOR_BODY]]:
+; WITH-PCLMUL-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; WITH-PCLMUL-NEXT: [[TMP2:%.*]] = getelementptr i64, ptr [[A]], i64 [[INDEX]]
+; WITH-PCLMUL-NEXT: [[TMP3:%.*]] = getelementptr i64, ptr [[B]], i64 [[INDEX]]
+; WITH-PCLMUL-NEXT: [[TMP4:%.*]] = getelementptr i64, ptr [[C]], i64 [[INDEX]]
+; WITH-PCLMUL-NEXT: [[TMP5:%.*]] = getelementptr i64, ptr [[TMP2]], i64 2
+; WITH-PCLMUL-NEXT: [[WIDE_LOAD:%.*]] = load <2 x i64>, ptr [[TMP2]], align 8
+; WITH-PCLMUL-NEXT: [[WIDE_LOAD5:%.*]] = load <2 x i64>, ptr [[TMP5]], align 8
+; WITH-PCLMUL-NEXT: [[TMP6:%.*]] = getelementptr i64, ptr [[TMP3]], i64 2
+; WITH-PCLMUL-NEXT: [[WIDE_LOAD6:%.*]] = load <2 x i64>, ptr [[TMP3]], align 8
+; WITH-PCLMUL-NEXT: [[WIDE_LOAD7:%.*]] = load <2 x i64>, ptr [[TMP6]], align 8
+; WITH-PCLMUL-NEXT: [[TMP7:%.*]] = call <2 x i64> @llvm.clmul.v2i64(<2 x i64> [[WIDE_LOAD]], <2 x i64> [[WIDE_LOAD6]])
+; WITH-PCLMUL-NEXT: [[TMP8:%.*]] = call <2 x i64> @llvm.clmul.v2i64(<2 x i64> [[WIDE_LOAD5]], <2 x i64> [[WIDE_LOAD7]])
+; WITH-PCLMUL-NEXT: [[TMP9:%.*]] = getelementptr i64, ptr [[TMP4]], i64 2
+; WITH-PCLMUL-NEXT: store <2 x i64> [[TMP7]], ptr [[TMP4]], align 8
+; WITH-PCLMUL-NEXT: store <2 x i64> [[TMP8]], ptr [[TMP9]], align 8
+; WITH-PCLMUL-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
+; WITH-PCLMUL-NEXT: [[TMP10:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
+; WITH-PCLMUL-NEXT: br i1 [[TMP10]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
+; WITH-PCLMUL: [[MIDDLE_BLOCK]]:
+; WITH-PCLMUL-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]]
+; WITH-PCLMUL-NEXT: br i1 [[CMP_N]], label %[[FOR_EXIT:.*]], label %[[SCALAR_PH]]
+; WITH-PCLMUL: [[SCALAR_PH]]:
+; WITH-PCLMUL-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_MEMCHECK]] ]
+; WITH-PCLMUL-NEXT: br label %[[FOR_BODY:.*]]
+; WITH-PCLMUL: [[FOR_BODY]]:
+; WITH-PCLMUL-NEXT: [[I:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[I_NEXT:%.*]], %[[FOR_BODY]] ]
+; WITH-PCLMUL-NEXT: [[PA:%.*]] = getelementptr i64, ptr [[A]], i64 [[I]]
+; WITH-PCLMUL-NEXT: [[PB:%.*]] = getelementptr i64, ptr [[B]], i64 [[I]]
+; WITH-PCLMUL-NEXT: [[PC:%.*]] = getelementptr i64, ptr [[C]], i64 [[I]]
+; WITH-PCLMUL-NEXT: [[VA:%.*]] = load i64, ptr [[PA]], align 8
+; WITH-PCLMUL-NEXT: [[VB:%.*]] = load i64, ptr [[PB]], align 8
+; WITH-PCLMUL-NEXT: [[R:%.*]] = call i64 @llvm.clmul.i64(i64 [[VA]], i64 [[VB]])
+; WITH-PCLMUL-NEXT: store i64 [[R]], ptr [[PC]], align 8
+; WITH-PCLMUL-NEXT: [[I_NEXT]] = add i64 [[I]], 1
+; WITH-PCLMUL-NEXT: [[CMP:%.*]] = icmp eq i64 [[I_NEXT]], [[N]]
+; WITH-PCLMUL-NEXT: br i1 [[CMP]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]
+; WITH-PCLMUL: [[FOR_EXIT]]:
+; WITH-PCLMUL-NEXT: ret void
+;
+; WITH-NO-PCLMUL-LABEL: define void @clmul_loop(
+; WITH-NO-PCLMUL-SAME: ptr [[A:%.*]], ptr [[B:%.*]], ptr [[C:%.*]], i64 [[N:%.*]]) #[[ATTR1:[0-9]+]] {
+; WITH-NO-PCLMUL-NEXT: [[ENTRY:.*]]:
+; WITH-NO-PCLMUL-NEXT: br label %[[FOR_BODY:.*]]
+; WITH-NO-PCLMUL: [[FOR_BODY]]:
+; WITH-NO-PCLMUL-NEXT: [[I:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[I_NEXT:%.*]], %[[FOR_BODY]] ]
+; WITH-NO-PCLMUL-NEXT: [[PA:%.*]] = getelementptr i64, ptr [[A]], i64 [[I]]
+; WITH-NO-PCLMUL-NEXT: [[PB:%.*]] = getelementptr i64, ptr [[B]], i64 [[I]]
+; WITH-NO-PCLMUL-NEXT: [[PC:%.*]] = getelementptr i64, ptr [[C]], i64 [[I]]
+; WITH-NO-PCLMUL-NEXT: [[VA:%.*]] = load i64, ptr [[PA]], align 8
+; WITH-NO-PCLMUL-NEXT: [[VB:%.*]] = load i64, ptr [[PB]], align 8
+; WITH-NO-PCLMUL-NEXT: [[R:%.*]] = call i64 @llvm.clmul.i64(i64 [[VA]], i64 [[VB]])
+; WITH-NO-PCLMUL-NEXT: store i64 [[R]], ptr [[PC]], align 8
+; WITH-NO-PCLMUL-NEXT: [[I_NEXT]] = add i64 [[I]], 1
+; WITH-NO-PCLMUL-NEXT: [[CMP:%.*]] = icmp eq i64 [[I_NEXT]], [[N]]
+; WITH-NO-PCLMUL-NEXT: br i1 [[CMP]], label %[[FOR_EXIT:.*]], label %[[FOR_BODY]]
+; WITH-NO-PCLMUL: [[FOR_EXIT]]:
+; WITH-NO-PCLMUL-NEXT: ret void
;
entry:
br label %for.body
@@ -89,8 +109,8 @@ for.exit:
}
;.
-; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}
-; CHECK: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}
-; CHECK: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}
-; CHECK: [[LOOP3]] = distinct !{[[LOOP3]], [[META1]]}
+; WITH-PCLMUL: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}
+; WITH-PCLMUL: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}
+; WITH-PCLMUL: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}
+; WITH-PCLMUL: [[LOOP3]] = distinct !{[[LOOP3]], [[META1]]}
;.
>From f2d5017e51e411d65e9db6f67ef387eb660b2145 Mon Sep 17 00:00:00 2001
From: pranshoe <pranshu.goyal71 at gmail.com>
Date: Mon, 16 Feb 2026 09:37:40 +0000
Subject: [PATCH 7/8] Regen checks for Intrinsic::clmul tests for X86/AArch64
---
.../Transforms/LoopVectorize/AArch64/clmul.ll | 50 ++++++++++++++++++-
.../Transforms/LoopVectorize/X86/clmul.ll | 6 +--
2 files changed, 51 insertions(+), 5 deletions(-)
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/clmul.ll b/llvm/test/Transforms/LoopVectorize/AArch64/clmul.ll
index d49b6b8885283..7979c4dd38ff9 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/clmul.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/clmul.ll
@@ -7,9 +7,49 @@ define void @clmul_loop(ptr %a, ptr %b, ptr %c, i64 %n) {
; CHECK-LABEL: define void @clmul_loop(
; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]], ptr [[C:%.*]], i64 [[N:%.*]]) #[[ATTR1:[0-9]+]] {
; CHECK-NEXT: [[ENTRY:.*]]:
+; CHECK-NEXT: [[B3:%.*]] = ptrtoaddr ptr [[B]] to i64
+; CHECK-NEXT: [[A2:%.*]] = ptrtoaddr ptr [[A]] to i64
+; CHECK-NEXT: [[C1:%.*]] = ptrtoaddr ptr [[C]] to i64
+; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 4
+; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_MEMCHECK:.*]]
+; CHECK: [[VECTOR_MEMCHECK]]:
+; CHECK-NEXT: [[TMP0:%.*]] = sub i64 [[C1]], [[A2]]
+; CHECK-NEXT: [[DIFF_CHECK:%.*]] = icmp ult i64 [[TMP0]], 32
+; CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[C1]], [[B3]]
+; CHECK-NEXT: [[DIFF_CHECK4:%.*]] = icmp ult i64 [[TMP1]], 32
+; CHECK-NEXT: [[CONFLICT_RDX:%.*]] = or i1 [[DIFF_CHECK]], [[DIFF_CHECK4]]
+; CHECK-NEXT: br i1 [[CONFLICT_RDX]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]
+; CHECK: [[VECTOR_PH]]:
+; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], 4
+; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]]
+; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK: [[VECTOR_BODY]]:
+; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i64, ptr [[A]], i64 [[INDEX]]
+; CHECK-NEXT: [[TMP3:%.*]] = getelementptr i64, ptr [[B]], i64 [[INDEX]]
+; CHECK-NEXT: [[TMP4:%.*]] = getelementptr i64, ptr [[C]], i64 [[INDEX]]
+; CHECK-NEXT: [[TMP5:%.*]] = getelementptr i64, ptr [[TMP2]], i64 2
+; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <2 x i64>, ptr [[TMP2]], align 8
+; CHECK-NEXT: [[WIDE_LOAD5:%.*]] = load <2 x i64>, ptr [[TMP5]], align 8
+; CHECK-NEXT: [[TMP6:%.*]] = getelementptr i64, ptr [[TMP3]], i64 2
+; CHECK-NEXT: [[WIDE_LOAD6:%.*]] = load <2 x i64>, ptr [[TMP3]], align 8
+; CHECK-NEXT: [[WIDE_LOAD7:%.*]] = load <2 x i64>, ptr [[TMP6]], align 8
+; CHECK-NEXT: [[TMP7:%.*]] = call <2 x i64> @llvm.clmul.v2i64(<2 x i64> [[WIDE_LOAD]], <2 x i64> [[WIDE_LOAD6]])
+; CHECK-NEXT: [[TMP8:%.*]] = call <2 x i64> @llvm.clmul.v2i64(<2 x i64> [[WIDE_LOAD5]], <2 x i64> [[WIDE_LOAD7]])
+; CHECK-NEXT: [[TMP9:%.*]] = getelementptr i64, ptr [[TMP4]], i64 2
+; CHECK-NEXT: store <2 x i64> [[TMP7]], ptr [[TMP4]], align 8
+; CHECK-NEXT: store <2 x i64> [[TMP8]], ptr [[TMP9]], align 8
+; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
+; CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
+; CHECK-NEXT: br i1 [[TMP10]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
+; CHECK: [[MIDDLE_BLOCK]]:
+; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]]
+; CHECK-NEXT: br i1 [[CMP_N]], label %[[FOR_EXIT:.*]], label %[[SCALAR_PH]]
+; CHECK: [[SCALAR_PH]]:
+; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_MEMCHECK]] ]
; CHECK-NEXT: br label %[[FOR_BODY:.*]]
; CHECK: [[FOR_BODY]]:
-; CHECK-NEXT: [[I:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[I_NEXT:%.*]], %[[FOR_BODY]] ]
+; CHECK-NEXT: [[I:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[I_NEXT:%.*]], %[[FOR_BODY]] ]
; CHECK-NEXT: [[PA:%.*]] = getelementptr i64, ptr [[A]], i64 [[I]]
; CHECK-NEXT: [[PB:%.*]] = getelementptr i64, ptr [[B]], i64 [[I]]
; CHECK-NEXT: [[PC:%.*]] = getelementptr i64, ptr [[C]], i64 [[I]]
@@ -19,7 +59,7 @@ define void @clmul_loop(ptr %a, ptr %b, ptr %c, i64 %n) {
; CHECK-NEXT: store i64 [[R]], ptr [[PC]], align 8
; CHECK-NEXT: [[I_NEXT]] = add i64 [[I]], 1
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i64 [[I_NEXT]], [[N]]
-; CHECK-NEXT: br i1 [[CMP]], label %[[FOR_EXIT:.*]], label %[[FOR_BODY]]
+; CHECK-NEXT: br i1 [[CMP]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]
; CHECK: [[FOR_EXIT]]:
; CHECK-NEXT: ret void
;
@@ -48,3 +88,9 @@ for.exit:
ret void
}
+;.
+; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}
+; CHECK: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}
+; CHECK: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}
+; CHECK: [[LOOP3]] = distinct !{[[LOOP3]], [[META1]]}
+;.
diff --git a/llvm/test/Transforms/LoopVectorize/X86/clmul.ll b/llvm/test/Transforms/LoopVectorize/X86/clmul.ll
index 20a154ef14152..3299dc06ff462 100644
--- a/llvm/test/Transforms/LoopVectorize/X86/clmul.ll
+++ b/llvm/test/Transforms/LoopVectorize/X86/clmul.ll
@@ -8,9 +8,9 @@ define void @clmul_loop(ptr %a, ptr %b, ptr %c, i64 %n){
; WITH-PCLMUL-LABEL: define void @clmul_loop(
; WITH-PCLMUL-SAME: ptr [[A:%.*]], ptr [[B:%.*]], ptr [[C:%.*]], i64 [[N:%.*]]) #[[ATTR1:[0-9]+]] {
; WITH-PCLMUL-NEXT: [[ENTRY:.*]]:
-; WITH-PCLMUL-NEXT: [[B3:%.*]] = ptrtoint ptr [[B]] to i64
-; WITH-PCLMUL-NEXT: [[A2:%.*]] = ptrtoint ptr [[A]] to i64
-; WITH-PCLMUL-NEXT: [[C1:%.*]] = ptrtoint ptr [[C]] to i64
+; WITH-PCLMUL-NEXT: [[B3:%.*]] = ptrtoaddr ptr [[B]] to i64
+; WITH-PCLMUL-NEXT: [[A2:%.*]] = ptrtoaddr ptr [[A]] to i64
+; WITH-PCLMUL-NEXT: [[C1:%.*]] = ptrtoaddr ptr [[C]] to i64
; WITH-PCLMUL-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 8
; WITH-PCLMUL-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_MEMCHECK:.*]]
; WITH-PCLMUL: [[VECTOR_MEMCHECK]]:
>From 0c0b4f8ed470164c8c9f2a51f48d020b216a5ea4 Mon Sep 17 00:00:00 2001
From: pranshoe <pranshu.goyal71 at gmail.com>
Date: Sat, 7 Mar 2026 06:12:56 +0000
Subject: [PATCH 8/8] Update patches as per after #182039
---
llvm/test/Transforms/LoopVectorize/AArch64/clmul.ll | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/clmul.ll b/llvm/test/Transforms/LoopVectorize/AArch64/clmul.ll
index 7979c4dd38ff9..e453fd4f12a3f 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/clmul.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/clmul.ll
@@ -10,7 +10,7 @@ define void @clmul_loop(ptr %a, ptr %b, ptr %c, i64 %n) {
; CHECK-NEXT: [[B3:%.*]] = ptrtoaddr ptr [[B]] to i64
; CHECK-NEXT: [[A2:%.*]] = ptrtoaddr ptr [[A]] to i64
; CHECK-NEXT: [[C1:%.*]] = ptrtoaddr ptr [[C]] to i64
-; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 4
+; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 6
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_MEMCHECK:.*]]
; CHECK: [[VECTOR_MEMCHECK]]:
; CHECK-NEXT: [[TMP0:%.*]] = sub i64 [[C1]], [[A2]]
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