[lldb] [llvm] [mlir] [IR] Split Br into UncondBr and CondBr (PR #184027)
Alexis Engelke via llvm-commits
llvm-commits at lists.llvm.org
Sat Mar 7 01:42:29 PST 2026
https://github.com/aengelke updated https://github.com/llvm/llvm-project/pull/184027
>From 66bed9c23d8073f36a9fa69cdb1b6d4834593cea Mon Sep 17 00:00:00 2001
From: Alexis Engelke <engelke at in.tum.de>
Date: Fri, 27 Feb 2026 10:50:01 +0000
Subject: [PATCH 1/8] [IR] Split Br into UncondBr and CondBr
BranchInst currently represents both unconditional and conditional
branches. However, these are quite different operations that are
often handled separately. Therefore, split them into separate opcodes
and classes to allow distinguishing these operations in the type system.
Additionally, this also slightly improves compile-time performance.
---
llvm/include/llvm-c/Core.h | 4 +-
.../llvm/Analysis/TargetTransformInfoImpl.h | 3 +-
llvm/include/llvm/CodeGen/BasicTTIImpl.h | 2 +-
.../llvm/CodeGen/GlobalISel/IRTranslator.h | 3 +-
llvm/include/llvm/IR/InstVisitor.h | 6 +
llvm/include/llvm/IR/Instruction.def | 161 +++++------
llvm/include/llvm/IR/Instructions.h | 251 ++++++++++++++----
.../Transforms/InstCombine/InstCombiner.h | 2 +-
llvm/lib/Analysis/ObjCARCInstKind.cpp | 3 +-
llvm/lib/Analysis/ValueTracking.cpp | 9 +-
llvm/lib/AsmParser/LLLexer.cpp | 2 +-
llvm/lib/Bitcode/Writer/BitcodeWriter.cpp | 21 +-
llvm/lib/CodeGen/CodeGenPrepare.cpp | 8 +-
llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp | 29 +-
llvm/lib/CodeGen/SelectionDAG/FastISel.cpp | 19 +-
.../SelectionDAG/SelectionDAGBuilder.cpp | 35 +--
.../SelectionDAG/SelectionDAGBuilder.h | 3 +-
llvm/lib/CodeGen/TargetLoweringBase.cpp | 3 +-
llvm/lib/CodeGen/TypePromotion.cpp | 3 +-
llvm/lib/FuzzMutate/RandomIRBuilder.cpp | 2 +-
llvm/lib/IR/Instruction.cpp | 3 +-
llvm/lib/IR/Instructions.cpp | 66 +++--
llvm/lib/IR/Metadata.cpp | 15 +-
llvm/lib/IR/ProfDataUtils.cpp | 3 +-
llvm/lib/SandboxIR/Context.cpp | 3 +-
llvm/lib/Target/AArch64/AArch64FastISel.cpp | 2 +-
.../AArch64/AArch64TargetTransformInfo.cpp | 9 +-
.../AMDGPU/AMDGPUTargetTransformInfo.cpp | 8 +-
.../Target/AMDGPU/R600TargetTransformInfo.cpp | 3 +-
llvm/lib/Target/ARM/ARMFastISel.cpp | 2 +-
llvm/lib/Target/Mips/MipsFastISel.cpp | 2 +-
llvm/lib/Target/PowerPC/PPCFastISel.cpp | 2 +-
.../Target/RISCV/RISCVTargetTransformInfo.cpp | 4 +-
.../WebAssembly/WebAssemblyFastISel.cpp | 2 +-
llvm/lib/Target/X86/X86FastISel.cpp | 2 +-
.../lib/Target/X86/X86TargetTransformInfo.cpp | 2 +-
llvm/lib/Transforms/IPO/Attributor.cpp | 3 +-
.../Transforms/IPO/AttributorAttributes.cpp | 18 +-
llvm/lib/Transforms/IPO/IROutliner.cpp | 8 +-
.../InstCombine/InstructionCombining.cpp | 2 +-
.../Transforms/Utils/BreakCriticalEdges.cpp | 3 +-
llvm/lib/Transforms/Utils/InlineFunction.cpp | 2 +-
llvm/lib/Transforms/Utils/SimplifyCFG.cpp | 13 +-
.../Vectorize/LoopVectorizationLegality.cpp | 3 +-
.../Transforms/Vectorize/LoopVectorize.cpp | 17 +-
llvm/lib/Transforms/Vectorize/VPlan.cpp | 2 +-
llvm/lib/Transforms/Vectorize/VPlan.h | 3 +-
.../lib/Transforms/Vectorize/VPlanRecipes.cpp | 5 +-
.../IR2Vec/Inputs/dummy_2D_vocab.json | 3 +-
.../Inputs/dummy_3D_nonzero_arg_vocab.json | 3 +-
.../Inputs/dummy_3D_nonzero_opc_vocab.json | 3 +-
.../Inputs/dummy_3D_nonzero_type_vocab.json | 3 +-
.../Inputs/reference_default_vocab_print.txt | 3 +-
.../Inputs/reference_wtd1_vocab_print.txt | 3 +-
.../Inputs/reference_wtd2_vocab_print.txt | 3 +-
llvm/test/Analysis/InstCount/instcount.ll | 3 +-
.../IRNormalizer/naming-args-instr-blocks.ll | 6 +-
.../IRNormalizer/naming-arguments.ll | 4 +-
llvm/test/Transforms/IRNormalizer/naming.ll | 12 +-
.../IRNormalizer/pass-parameters.ll | 4 +-
.../regression-convergence-tokens.ll | 6 +-
.../IRNormalizer/regression-infinite-loop.ll | 178 ++++++-------
.../IRNormalizer/reordering-basic.ll | 14 +-
.../Transforms/IRNormalizer/reordering.ll | 36 +--
llvm/test/tools/llvm-ir2vec/entities.ll | 223 ++++++++--------
llvm/test/tools/llvm-ir2vec/triplets.ll | 76 +++---
llvm/tools/llvm-c-test/echo.cpp | 15 +-
llvm/unittests/Analysis/IR2VecTest.cpp | 33 +--
mlir/lib/Target/LLVMIR/ModuleImport.cpp | 22 +-
69 files changed, 812 insertions(+), 617 deletions(-)
diff --git a/llvm/include/llvm-c/Core.h b/llvm/include/llvm-c/Core.h
index 3fa2801e4b4bd..de1b5aa092ac6 100644
--- a/llvm/include/llvm-c/Core.h
+++ b/llvm/include/llvm-c/Core.h
@@ -61,7 +61,9 @@ LLVM_C_EXTERN_C_BEGIN
typedef enum {
/* Terminator Instructions */
LLVMRet = 1,
- LLVMBr = 2,
+ /* removed 2 due to API changes */
+ LLVMUncondBr = 70,
+ LLVMCondBr = 71,
LLVMSwitch = 3,
LLVMIndirectBr = 4,
LLVMInvoke = 5,
diff --git a/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h b/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
index e062b70be6b59..b0f2f718e552d 100644
--- a/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
+++ b/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
@@ -1452,7 +1452,8 @@ class TargetTransformInfoImplCRTPBase : public TargetTransformInfoImplBase {
IntrinsicCostAttributes CostAttrs(Intrinsic->getIntrinsicID(), *CB);
return TargetTTI->getIntrinsicInstrCost(CostAttrs, CostKind);
}
- case Instruction::Br:
+ case Instruction::UncondBr:
+ case Instruction::CondBr:
case Instruction::Ret:
case Instruction::PHI:
case Instruction::Switch:
diff --git a/llvm/include/llvm/CodeGen/BasicTTIImpl.h b/llvm/include/llvm/CodeGen/BasicTTIImpl.h
index 6dcb6f0062a08..f393bd7f9e6f7 100644
--- a/llvm/include/llvm/CodeGen/BasicTTIImpl.h
+++ b/llvm/include/llvm/CodeGen/BasicTTIImpl.h
@@ -255,7 +255,7 @@ class BasicTTIImplBase : public TargetTransformInfoImplCRTPBase<T> {
getScalarizationOverhead(
FixedVectorType::get(Type::getInt1Ty(DataTy->getContext()), VF),
/*Insert=*/false, /*Extract=*/true, CostKind) +
- VF * (thisT()->getCFInstrCost(Instruction::Br, CostKind) +
+ VF * (thisT()->getCFInstrCost(Instruction::CondBr, CostKind) +
thisT()->getCFInstrCost(Instruction::PHI, CostKind));
}
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/IRTranslator.h b/llvm/include/llvm/CodeGen/GlobalISel/IRTranslator.h
index 2f3f55a58a517..6d916b76cee55 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/IRTranslator.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/IRTranslator.h
@@ -380,7 +380,8 @@ class IRTranslator : public MachineFunctionPass {
/// Translate branch (br) instruction.
/// \pre \p U is a branch instruction.
- bool translateBr(const User &U, MachineIRBuilder &MIRBuilder);
+ bool translateUncondBr(const User &U, MachineIRBuilder &MIRBuilder);
+ bool translateCondBr(const User &U, MachineIRBuilder &MIRBuilder);
// Begin switch lowering functions.
bool emitJumpTableHeader(SwitchCG::JumpTable &JT,
diff --git a/llvm/include/llvm/IR/InstVisitor.h b/llvm/include/llvm/IR/InstVisitor.h
index 8e4dc647e5230..e58c7745c87f9 100644
--- a/llvm/include/llvm/IR/InstVisitor.h
+++ b/llvm/include/llvm/IR/InstVisitor.h
@@ -221,6 +221,12 @@ class InstVisitor {
RetTy visitReturnInst(ReturnInst &I) {
return static_cast<SubClass *>(this)->visitTerminator(I);
}
+ RetTy visitUncondBrInst(UncondBrInst &I) {
+ return static_cast<SubClass *>(this)->visitBranchInst(I);
+ }
+ RetTy visitCondBrInst(CondBrInst &I) {
+ return static_cast<SubClass *>(this)->visitBranchInst(I);
+ }
RetTy visitBranchInst(BranchInst &I) {
return static_cast<SubClass *>(this)->visitTerminator(I);
}
diff --git a/llvm/include/llvm/IR/Instruction.def b/llvm/include/llvm/IR/Instruction.def
index face6a93ec7d5..89d214868e16b 100644
--- a/llvm/include/llvm/IR/Instruction.def
+++ b/llvm/include/llvm/IR/Instruction.def
@@ -125,101 +125,102 @@
//
FIRST_TERM_INST ( 1)
HANDLE_TERM_INST ( 1, Ret , ReturnInst)
-HANDLE_TERM_INST ( 2, Br , BranchInst)
-HANDLE_TERM_INST ( 3, Switch , SwitchInst)
-HANDLE_TERM_INST ( 4, IndirectBr , IndirectBrInst)
-HANDLE_TERM_INST ( 5, Invoke , InvokeInst)
-HANDLE_TERM_INST ( 6, Resume , ResumeInst)
-HANDLE_TERM_INST ( 7, Unreachable , UnreachableInst)
-HANDLE_TERM_INST ( 8, CleanupRet , CleanupReturnInst)
-HANDLE_TERM_INST ( 9, CatchRet , CatchReturnInst)
-HANDLE_TERM_INST (10, CatchSwitch , CatchSwitchInst)
-HANDLE_TERM_INST (11, CallBr , CallBrInst) // A call-site terminator
- LAST_TERM_INST (11)
+HANDLE_TERM_INST ( 2, UncondBr , UncondBrInst)
+HANDLE_TERM_INST ( 3, CondBr , CondBrInst)
+HANDLE_TERM_INST ( 4, Switch , SwitchInst)
+HANDLE_TERM_INST ( 5, IndirectBr , IndirectBrInst)
+HANDLE_TERM_INST ( 6, Invoke , InvokeInst)
+HANDLE_TERM_INST ( 7, Resume , ResumeInst)
+HANDLE_TERM_INST ( 8, Unreachable , UnreachableInst)
+HANDLE_TERM_INST ( 9, CleanupRet , CleanupReturnInst)
+HANDLE_TERM_INST (10, CatchRet , CatchReturnInst)
+HANDLE_TERM_INST (11, CatchSwitch , CatchSwitchInst)
+HANDLE_TERM_INST (12, CallBr , CallBrInst) // A call-site terminator
+ LAST_TERM_INST (12)
// Standard unary operators...
- FIRST_UNARY_INST(12)
-HANDLE_UNARY_INST(12, FNeg , UnaryOperator)
- LAST_UNARY_INST(12)
+ FIRST_UNARY_INST(13)
+HANDLE_UNARY_INST(13, FNeg , UnaryOperator)
+ LAST_UNARY_INST(13)
// Standard binary operators...
- FIRST_BINARY_INST(13)
-HANDLE_BINARY_INST(13, Add , BinaryOperator)
-HANDLE_BINARY_INST(14, FAdd , BinaryOperator)
-HANDLE_BINARY_INST(15, Sub , BinaryOperator)
-HANDLE_BINARY_INST(16, FSub , BinaryOperator)
-HANDLE_BINARY_INST(17, Mul , BinaryOperator)
-HANDLE_BINARY_INST(18, FMul , BinaryOperator)
-HANDLE_BINARY_INST(19, UDiv , BinaryOperator)
-HANDLE_BINARY_INST(20, SDiv , BinaryOperator)
-HANDLE_BINARY_INST(21, FDiv , BinaryOperator)
-HANDLE_BINARY_INST(22, URem , BinaryOperator)
-HANDLE_BINARY_INST(23, SRem , BinaryOperator)
-HANDLE_BINARY_INST(24, FRem , BinaryOperator)
+ FIRST_BINARY_INST(14)
+HANDLE_BINARY_INST(14, Add , BinaryOperator)
+HANDLE_BINARY_INST(15, FAdd , BinaryOperator)
+HANDLE_BINARY_INST(16, Sub , BinaryOperator)
+HANDLE_BINARY_INST(17, FSub , BinaryOperator)
+HANDLE_BINARY_INST(18, Mul , BinaryOperator)
+HANDLE_BINARY_INST(19, FMul , BinaryOperator)
+HANDLE_BINARY_INST(20, UDiv , BinaryOperator)
+HANDLE_BINARY_INST(21, SDiv , BinaryOperator)
+HANDLE_BINARY_INST(22, FDiv , BinaryOperator)
+HANDLE_BINARY_INST(23, URem , BinaryOperator)
+HANDLE_BINARY_INST(24, SRem , BinaryOperator)
+HANDLE_BINARY_INST(25, FRem , BinaryOperator)
// Logical operators (integer operands)
-HANDLE_BINARY_INST(25, Shl , BinaryOperator) // Shift left (logical)
-HANDLE_BINARY_INST(26, LShr , BinaryOperator) // Shift right (logical)
-HANDLE_BINARY_INST(27, AShr , BinaryOperator) // Shift right (arithmetic)
-HANDLE_BINARY_INST(28, And , BinaryOperator)
-HANDLE_BINARY_INST(29, Or , BinaryOperator)
-HANDLE_BINARY_INST(30, Xor , BinaryOperator)
- LAST_BINARY_INST(30)
+HANDLE_BINARY_INST(26, Shl , BinaryOperator) // Shift left (logical)
+HANDLE_BINARY_INST(27, LShr , BinaryOperator) // Shift right (logical)
+HANDLE_BINARY_INST(28, AShr , BinaryOperator) // Shift right (arithmetic)
+HANDLE_BINARY_INST(29, And , BinaryOperator)
+HANDLE_BINARY_INST(30, Or , BinaryOperator)
+HANDLE_BINARY_INST(31, Xor , BinaryOperator)
+ LAST_BINARY_INST(31)
// Memory operators...
- FIRST_MEMORY_INST(31)
-HANDLE_MEMORY_INST(31, Alloca, AllocaInst) // Stack management
-HANDLE_MEMORY_INST(32, Load , LoadInst ) // Memory manipulation instrs
-HANDLE_MEMORY_INST(33, Store , StoreInst )
-HANDLE_MEMORY_INST(34, GetElementPtr, GetElementPtrInst)
-HANDLE_MEMORY_INST(35, Fence , FenceInst )
-HANDLE_MEMORY_INST(36, AtomicCmpXchg , AtomicCmpXchgInst )
-HANDLE_MEMORY_INST(37, AtomicRMW , AtomicRMWInst )
- LAST_MEMORY_INST(37)
+ FIRST_MEMORY_INST(32)
+HANDLE_MEMORY_INST(32, Alloca, AllocaInst) // Stack management
+HANDLE_MEMORY_INST(33, Load , LoadInst ) // Memory manipulation instrs
+HANDLE_MEMORY_INST(34, Store , StoreInst )
+HANDLE_MEMORY_INST(35, GetElementPtr, GetElementPtrInst)
+HANDLE_MEMORY_INST(36, Fence , FenceInst )
+HANDLE_MEMORY_INST(37, AtomicCmpXchg , AtomicCmpXchgInst )
+HANDLE_MEMORY_INST(38, AtomicRMW , AtomicRMWInst )
+ LAST_MEMORY_INST(38)
// Cast operators ...
// NOTE: The order matters here because CastInst::isEliminableCastPair
// NOTE: (see Instructions.cpp) encodes a table based on this ordering.
- FIRST_CAST_INST(38)
-HANDLE_CAST_INST(38, Trunc , TruncInst ) // Truncate integers
-HANDLE_CAST_INST(39, ZExt , ZExtInst ) // Zero extend integers
-HANDLE_CAST_INST(40, SExt , SExtInst ) // Sign extend integers
-HANDLE_CAST_INST(41, FPToUI , FPToUIInst ) // floating point -> UInt
-HANDLE_CAST_INST(42, FPToSI , FPToSIInst ) // floating point -> SInt
-HANDLE_CAST_INST(43, UIToFP , UIToFPInst ) // UInt -> floating point
-HANDLE_CAST_INST(44, SIToFP , SIToFPInst ) // SInt -> floating point
-HANDLE_CAST_INST(45, FPTrunc , FPTruncInst ) // Truncate floating point
-HANDLE_CAST_INST(46, FPExt , FPExtInst ) // Extend floating point
-HANDLE_CAST_INST(47, PtrToInt, PtrToIntInst) // Pointer -> Integer (bitcast)
-HANDLE_CAST_INST(48, PtrToAddr, PtrToAddrInst) // Pointer -> Address
-HANDLE_CAST_INST(49, IntToPtr, IntToPtrInst) // Integer -> Pointer
-HANDLE_CAST_INST(50, BitCast , BitCastInst ) // Type cast
-HANDLE_CAST_INST(51, AddrSpaceCast, AddrSpaceCastInst) // addrspace cast
- LAST_CAST_INST(51)
+ FIRST_CAST_INST(39)
+HANDLE_CAST_INST(39, Trunc , TruncInst ) // Truncate integers
+HANDLE_CAST_INST(40, ZExt , ZExtInst ) // Zero extend integers
+HANDLE_CAST_INST(41, SExt , SExtInst ) // Sign extend integers
+HANDLE_CAST_INST(42, FPToUI , FPToUIInst ) // floating point -> UInt
+HANDLE_CAST_INST(43, FPToSI , FPToSIInst ) // floating point -> SInt
+HANDLE_CAST_INST(44, UIToFP , UIToFPInst ) // UInt -> floating point
+HANDLE_CAST_INST(45, SIToFP , SIToFPInst ) // SInt -> floating point
+HANDLE_CAST_INST(46, FPTrunc , FPTruncInst ) // Truncate floating point
+HANDLE_CAST_INST(47, FPExt , FPExtInst ) // Extend floating point
+HANDLE_CAST_INST(48, PtrToInt, PtrToIntInst) // Pointer -> Integer (bitcast)
+HANDLE_CAST_INST(49, PtrToAddr, PtrToAddrInst) // Pointer -> Address
+HANDLE_CAST_INST(50, IntToPtr, IntToPtrInst) // Integer -> Pointer
+HANDLE_CAST_INST(51, BitCast , BitCastInst ) // Type cast
+HANDLE_CAST_INST(52, AddrSpaceCast, AddrSpaceCastInst) // addrspace cast
+ LAST_CAST_INST(52)
- FIRST_FUNCLETPAD_INST(52)
-HANDLE_FUNCLETPAD_INST(52, CleanupPad, CleanupPadInst)
-HANDLE_FUNCLETPAD_INST(53, CatchPad , CatchPadInst)
- LAST_FUNCLETPAD_INST(53)
+ FIRST_FUNCLETPAD_INST(53)
+HANDLE_FUNCLETPAD_INST(53, CleanupPad, CleanupPadInst)
+HANDLE_FUNCLETPAD_INST(54, CatchPad , CatchPadInst)
+ LAST_FUNCLETPAD_INST(54)
// Other operators...
- FIRST_OTHER_INST(54)
-HANDLE_OTHER_INST(54, ICmp , ICmpInst ) // Integer comparison instruction
-HANDLE_OTHER_INST(55, FCmp , FCmpInst ) // Floating point comparison instr.
-HANDLE_OTHER_INST(56, PHI , PHINode ) // PHI node instruction
-HANDLE_OTHER_INST(57, Call , CallInst ) // Call a function
-HANDLE_OTHER_INST(58, Select , SelectInst ) // select instruction
-HANDLE_USER_INST (59, UserOp1, Instruction) // May be used internally in a pass
-HANDLE_USER_INST (60, UserOp2, Instruction) // Internal to passes only
-HANDLE_OTHER_INST(61, VAArg , VAArgInst ) // vaarg instruction
-HANDLE_OTHER_INST(62, ExtractElement, ExtractElementInst)// extract from vector
-HANDLE_OTHER_INST(63, InsertElement, InsertElementInst) // insert into vector
-HANDLE_OTHER_INST(64, ShuffleVector, ShuffleVectorInst) // shuffle two vectors.
-HANDLE_OTHER_INST(65, ExtractValue, ExtractValueInst)// extract from aggregate
-HANDLE_OTHER_INST(66, InsertValue, InsertValueInst) // insert into aggregate
-HANDLE_OTHER_INST(67, LandingPad, LandingPadInst) // Landing pad instruction.
-HANDLE_OTHER_INST(68, Freeze, FreezeInst) // Freeze instruction.
- LAST_OTHER_INST(68)
+ FIRST_OTHER_INST(55)
+HANDLE_OTHER_INST(55, ICmp , ICmpInst ) // Integer comparison instruction
+HANDLE_OTHER_INST(56, FCmp , FCmpInst ) // Floating point comparison instr.
+HANDLE_OTHER_INST(57, PHI , PHINode ) // PHI node instruction
+HANDLE_OTHER_INST(58, Call , CallInst ) // Call a function
+HANDLE_OTHER_INST(59, Select , SelectInst ) // select instruction
+HANDLE_USER_INST (60, UserOp1, Instruction) // May be used internally in a pass
+HANDLE_USER_INST (61, UserOp2, Instruction) // Internal to passes only
+HANDLE_OTHER_INST(62, VAArg , VAArgInst ) // vaarg instruction
+HANDLE_OTHER_INST(63, ExtractElement, ExtractElementInst)// extract from vector
+HANDLE_OTHER_INST(64, InsertElement, InsertElementInst) // insert into vector
+HANDLE_OTHER_INST(65, ShuffleVector, ShuffleVectorInst) // shuffle two vectors.
+HANDLE_OTHER_INST(66, ExtractValue, ExtractValueInst)// extract from aggregate
+HANDLE_OTHER_INST(67, InsertValue, InsertValueInst) // insert into aggregate
+HANDLE_OTHER_INST(68, LandingPad, LandingPadInst) // Landing pad instruction.
+HANDLE_OTHER_INST(69, Freeze, FreezeInst) // Freeze instruction.
+ LAST_OTHER_INST(69)
#undef FIRST_TERM_INST
#undef HANDLE_TERM_INST
diff --git a/llvm/include/llvm/IR/Instructions.h b/llvm/include/llvm/IR/Instructions.h
index d4ea74c05ae62..8f1014594a7b8 100644
--- a/llvm/include/llvm/IR/Instructions.h
+++ b/llvm/include/llvm/IR/Instructions.h
@@ -3056,32 +3056,10 @@ DEFINE_TRANSPARENT_OPERAND_ACCESSORS(ReturnInst, Value)
/// Conditional or Unconditional Branch instruction.
///
class BranchInst : public Instruction {
- /// Ops list - Branches are strange. The operands are ordered:
- /// [Cond, FalseDest,] TrueDest. This makes some accessors faster because
- /// they don't have to check for cond/uncond branchness. These are mostly
- /// accessed relative from op_end().
- BranchInst(const BranchInst &BI, AllocInfo AllocInfo);
- // BranchInst constructors (where {B, T, F} are blocks, and C is a condition):
- // BranchInst(BB *B) - 'br B'
- // BranchInst(BB* T, BB *F, Value *C) - 'br C, T, F'
- // BranchInst(BB* B, Iter It) - 'br B' insert before I
- // BranchInst(BB* T, BB *F, Value *C, Iter It) - 'br C, T, F', insert before I
- // BranchInst(BB* B, Inst *I) - 'br B' insert before I
- // BranchInst(BB* T, BB *F, Value *C, Inst *I) - 'br C, T, F', insert before I
- // BranchInst(BB* B, BB *I) - 'br B' insert at end
- // BranchInst(BB* T, BB *F, Value *C, BB *I) - 'br C, T, F', insert at end
- LLVM_ABI explicit BranchInst(BasicBlock *IfTrue, AllocInfo AllocInfo,
- InsertPosition InsertBefore);
- LLVM_ABI BranchInst(BasicBlock *IfTrue, BasicBlock *IfFalse, Value *Cond,
- AllocInfo AllocInfo, InsertPosition InsertBefore);
-
- void AssertOK();
-
protected:
- // Note: Instruction needs to be a friend here to call cloneImpl.
- friend class Instruction;
-
- LLVM_ABI BranchInst *cloneImpl() const;
+ BranchInst(Type *Ty, unsigned Opcode, AllocInfo AllocInfo,
+ InsertPosition InsertBefore = nullptr)
+ : Instruction(Ty, Opcode, AllocInfo, InsertBefore) {}
public:
/// Iterator type that casts an operand to a basic block.
@@ -3112,34 +3090,20 @@ class BranchInst : public Instruction {
};
static BranchInst *Create(BasicBlock *IfTrue,
- InsertPosition InsertBefore = nullptr) {
- IntrusiveOperandsAllocMarker AllocMarker{1};
- return new (AllocMarker) BranchInst(IfTrue, AllocMarker, InsertBefore);
- }
+ InsertPosition InsertBefore = nullptr);
static BranchInst *Create(BasicBlock *IfTrue, BasicBlock *IfFalse,
- Value *Cond,
- InsertPosition InsertBefore = nullptr) {
- IntrusiveOperandsAllocMarker AllocMarker{3};
- return new (AllocMarker)
- BranchInst(IfTrue, IfFalse, Cond, AllocMarker, InsertBefore);
- }
+ Value *Cond, InsertPosition InsertBefore = nullptr);
/// Transparently provide more efficient getOperand methods.
DECLARE_TRANSPARENT_OPERAND_ACCESSORS(Value);
- bool isUnconditional() const { return getNumOperands() == 1; }
- bool isConditional() const { return getNumOperands() == 3; }
-
- Value *getCondition() const {
- assert(isConditional() && "Cannot get condition of an uncond branch!");
- return Op<-3>();
- }
+ // Defined out-of-line below to access CondBrInst.
+ bool isUnconditional() const;
+ bool isConditional() const;
- void setCondition(Value *V) {
- assert(isConditional() && "Cannot set condition of unconditional branch!");
- Op<-3>() = V;
- }
+ Value *getCondition() const;
+ void setCondition(Value *V);
unsigned getNumSuccessors() const { return 1+isConditional(); }
@@ -3158,7 +3122,7 @@ class BranchInst : public Instruction {
/// Swaps the successors of the branch instruction. This also swaps any
/// branch weight metadata associated with the instruction so that it
/// continues to map correctly to each operand.
- LLVM_ABI void swapSuccessors();
+ void swapSuccessors();
iterator_range<succ_op_iterator> successors() {
return make_range(
@@ -3174,7 +3138,8 @@ class BranchInst : public Instruction {
// Methods for support type inquiry through isa, cast, and dyn_cast:
static bool classof(const Instruction *I) {
- return (I->getOpcode() == Instruction::Br);
+ return (I->getOpcode() == Instruction::UncondBr ||
+ I->getOpcode() == Instruction::CondBr);
}
static bool classof(const Value *V) {
return isa<Instruction>(V) && classof(cast<Instruction>(V));
@@ -3186,6 +3151,196 @@ struct OperandTraits<BranchInst> : public VariadicOperandTraits<BranchInst> {};
DEFINE_TRANSPARENT_OPERAND_ACCESSORS(BranchInst, Value)
+//===----------------------------------------------------------------------===//
+// UncondBrInst Class
+//===----------------------------------------------------------------------===//
+
+//===---------------------------------------------------------------------------
+/// Unconditional Branch instruction.
+///
+class UncondBrInst : public BranchInst {
+ UncondBrInst(const UncondBrInst &BI, AllocInfo AllocInfo);
+ LLVM_ABI explicit UncondBrInst(BasicBlock *IfTrue, AllocInfo AllocInfo,
+ InsertPosition InsertBefore);
+
+protected:
+ // Note: Instruction needs to be a friend here to call cloneImpl.
+ friend class Instruction;
+
+ LLVM_ABI UncondBrInst *cloneImpl() const;
+
+public:
+ static UncondBrInst *Create(BasicBlock *IfTrue,
+ InsertPosition InsertBefore = nullptr) {
+ IntrusiveOperandsAllocMarker AllocMarker{1};
+ return new (AllocMarker) UncondBrInst(IfTrue, AllocMarker, InsertBefore);
+ }
+
+ /// Transparently provide more efficient getOperand methods.
+ DECLARE_TRANSPARENT_OPERAND_ACCESSORS(Value);
+
+private:
+ // Hide methods.
+ using BranchInst::getCondition;
+ using BranchInst::isConditional;
+ using BranchInst::isUnconditional;
+ using BranchInst::setCondition;
+ using BranchInst::swapSuccessors;
+
+public:
+ unsigned getNumSuccessors() const { return 1; }
+
+ BasicBlock *getSuccessor(unsigned i = 0) const {
+ assert(i == 0 && "Successor # out of range for Branch!");
+ return cast_or_null<BasicBlock>(Op<-1>().get());
+ }
+
+ void setSuccessor(BasicBlock *NewSucc) { Op<-1>() = NewSucc; }
+ void setSuccessor(unsigned idx, BasicBlock *NewSucc) {
+ assert(idx == 0 && "Successor # out of range for Branch!");
+ Op<-1>() = NewSucc;
+ }
+
+ iterator_range<succ_op_iterator> successors() {
+ return make_range(succ_op_iterator(value_op_begin()),
+ succ_op_iterator(value_op_end()));
+ }
+
+ iterator_range<const_succ_op_iterator> successors() const {
+ return make_range(const_succ_op_iterator(value_op_begin()),
+ const_succ_op_iterator(value_op_end()));
+ }
+
+ // Methods for support type inquiry through isa, cast, and dyn_cast:
+ static bool classof(const Instruction *I) {
+ return (I->getOpcode() == Instruction::UncondBr);
+ }
+ static bool classof(const Value *V) {
+ return isa<Instruction>(V) && classof(cast<Instruction>(V));
+ }
+};
+
+template <>
+struct OperandTraits<UncondBrInst>
+ : public FixedNumOperandTraits<UncondBrInst, 1> {};
+
+DEFINE_TRANSPARENT_OPERAND_ACCESSORS(UncondBrInst, Value)
+
+//===----------------------------------------------------------------------===//
+// CondBrInst Class
+//===----------------------------------------------------------------------===//
+
+//===---------------------------------------------------------------------------
+/// Conditional or Unconditional Branch instruction.
+///
+class CondBrInst : public BranchInst {
+ CondBrInst(const CondBrInst &BI, AllocInfo AllocInfo);
+ LLVM_ABI CondBrInst(BasicBlock *IfTrue, BasicBlock *IfFalse, Value *Cond,
+ AllocInfo AllocInfo, InsertPosition InsertBefore);
+
+ void AssertOK();
+
+protected:
+ // Note: Instruction needs to be a friend here to call cloneImpl.
+ friend class Instruction;
+
+ LLVM_ABI CondBrInst *cloneImpl() const;
+
+private:
+ // Hide methods.
+ using BranchInst::isConditional;
+ using BranchInst::isUnconditional;
+
+public:
+ static CondBrInst *Create(BasicBlock *IfTrue, BasicBlock *IfFalse,
+ Value *Cond,
+ InsertPosition InsertBefore = nullptr) {
+ IntrusiveOperandsAllocMarker AllocMarker{3};
+ return new (AllocMarker)
+ CondBrInst(IfTrue, IfFalse, Cond, AllocMarker, InsertBefore);
+ }
+
+ /// Transparently provide more efficient getOperand methods.
+ DECLARE_TRANSPARENT_OPERAND_ACCESSORS(Value);
+
+ Value *getCondition() const { return Op<-3>(); }
+ void setCondition(Value *V) { Op<-3>() = V; }
+
+ unsigned getNumSuccessors() const { return 2; }
+
+ BasicBlock *getSuccessor(unsigned i) const {
+ assert(i < getNumSuccessors() && "Successor # out of range for Branch!");
+ return cast_or_null<BasicBlock>((&Op<-1>() - i)->get());
+ }
+
+ void setSuccessor(unsigned idx, BasicBlock *NewSucc) {
+ assert(idx < getNumSuccessors() && "Successor # out of range for Branch!");
+ *(&Op<-1>() - idx) = NewSucc;
+ }
+
+ /// Swap the successors of this branch instruction.
+ ///
+ /// Swaps the successors of the branch instruction. This also swaps any
+ /// branch weight metadata associated with the instruction so that it
+ /// continues to map correctly to each operand.
+ LLVM_ABI void swapSuccessors();
+
+ iterator_range<succ_op_iterator> successors() {
+ return make_range(succ_op_iterator(std::next(value_op_begin())),
+ succ_op_iterator(value_op_end()));
+ }
+
+ iterator_range<const_succ_op_iterator> successors() const {
+ return make_range(const_succ_op_iterator(std::next(value_op_begin())),
+ const_succ_op_iterator(value_op_end()));
+ }
+
+ // Methods for support type inquiry through isa, cast, and dyn_cast:
+ static bool classof(const Instruction *I) {
+ return (I->getOpcode() == Instruction::CondBr);
+ }
+ static bool classof(const Value *V) {
+ return isa<Instruction>(V) && classof(cast<Instruction>(V));
+ }
+};
+
+template <>
+struct OperandTraits<CondBrInst> : public FixedNumOperandTraits<CondBrInst, 3> {
+};
+
+DEFINE_TRANSPARENT_OPERAND_ACCESSORS(CondBrInst, Value)
+
+//===----------------------------------------------------------------------===//
+// BranchInst Out-Of-Line Functions
+//===----------------------------------------------------------------------===//
+
+inline BranchInst *BranchInst::Create(BasicBlock *IfTrue,
+ InsertPosition InsertBefore) {
+ return UncondBrInst::Create(IfTrue, InsertBefore);
+}
+
+inline BranchInst *BranchInst::Create(BasicBlock *IfTrue, BasicBlock *IfFalse,
+ Value *Cond,
+ InsertPosition InsertBefore) {
+ return CondBrInst::Create(IfTrue, IfFalse, Cond, InsertBefore);
+}
+
+inline bool BranchInst::isConditional() const { return isa<CondBrInst>(this); }
+inline bool BranchInst::isUnconditional() const {
+ return isa<UncondBrInst>(this);
+}
+
+inline Value *BranchInst::getCondition() const {
+ return cast<CondBrInst>(this)->getCondition();
+}
+inline void BranchInst::setCondition(Value *V) {
+ cast<CondBrInst>(this)->setCondition(V);
+}
+
+inline void BranchInst::swapSuccessors() {
+ cast<CondBrInst>(this)->swapSuccessors();
+}
+
//===----------------------------------------------------------------------===//
// SwitchInst Class
//===----------------------------------------------------------------------===//
diff --git a/llvm/include/llvm/Transforms/InstCombine/InstCombiner.h b/llvm/include/llvm/Transforms/InstCombine/InstCombiner.h
index 1563c9319df87..6de06addac71c 100644
--- a/llvm/include/llvm/Transforms/InstCombine/InstCombiner.h
+++ b/llvm/include/llvm/Transforms/InstCombine/InstCombiner.h
@@ -257,7 +257,7 @@ class LLVM_LIBRARY_VISIBILITY InstCombiner {
if (shouldAvoidAbsorbingNotIntoSelect(*cast<SelectInst>(I)))
return false;
break;
- case Instruction::Br:
+ case Instruction::CondBr:
assert(U.getOperandNo() == 0 && "Must be branching on that value.");
break; // Free to invert by swapping true/false values/destinations.
case Instruction::Xor: // Can invert 'xor' if it's a 'not', by ignoring
diff --git a/llvm/lib/Analysis/ObjCARCInstKind.cpp b/llvm/lib/Analysis/ObjCARCInstKind.cpp
index d177ee056a93a..fcc2c00725079 100644
--- a/llvm/lib/Analysis/ObjCARCInstKind.cpp
+++ b/llvm/lib/Analysis/ObjCARCInstKind.cpp
@@ -244,7 +244,8 @@ ARCInstKind llvm::objcarc::GetARCInstKind(const Value *V) {
case Instruction::Select:
case Instruction::PHI:
case Instruction::Ret:
- case Instruction::Br:
+ case Instruction::UncondBr:
+ case Instruction::CondBr:
case Instruction::Switch:
case Instruction::IndirectBr:
case Instruction::Alloca:
diff --git a/llvm/lib/Analysis/ValueTracking.cpp b/llvm/lib/Analysis/ValueTracking.cpp
index 2684b41cd1e5d..4ece6cb6f75a0 100644
--- a/llvm/lib/Analysis/ValueTracking.cpp
+++ b/llvm/lib/Analysis/ValueTracking.cpp
@@ -7161,7 +7161,8 @@ bool llvm::isSafeToSpeculativelyExecuteWithOpcode(
case Instruction::PHI:
case Instruction::Store:
case Instruction::Ret:
- case Instruction::Br:
+ case Instruction::UncondBr:
+ case Instruction::CondBr:
case Instruction::IndirectBr:
case Instruction::Switch:
case Instruction::Unreachable:
@@ -8116,12 +8117,10 @@ static bool handleGuaranteedWellDefinedOps(const Instruction *I,
if (Handle(cast<SwitchInst>(I)->getCondition()))
return true;
break;
- case Instruction::Br: {
- auto *BR = cast<BranchInst>(I);
- if (BR->isConditional() && Handle(BR->getCondition()))
+ case Instruction::CondBr:
+ if (Handle(cast<CondBrInst>(I)->getCondition()))
return true;
break;
- }
default:
break;
}
diff --git a/llvm/lib/AsmParser/LLLexer.cpp b/llvm/lib/AsmParser/LLLexer.cpp
index 8d20ff72a8505..cf3e79e932abf 100644
--- a/llvm/lib/AsmParser/LLLexer.cpp
+++ b/llvm/lib/AsmParser/LLLexer.cpp
@@ -543,6 +543,7 @@ lltok::Kind LLLexer::LexIdentifier() {
KEYWORD(true); KEYWORD(false);
KEYWORD(declare); KEYWORD(define);
KEYWORD(global); KEYWORD(constant);
+ KEYWORD(br);
KEYWORD(dso_local);
KEYWORD(dso_preemptable);
@@ -950,7 +951,6 @@ lltok::Kind LLLexer::LexIdentifier() {
INSTKEYWORD(select, Select);
INSTKEYWORD(va_arg, VAArg);
INSTKEYWORD(ret, Ret);
- INSTKEYWORD(br, Br);
INSTKEYWORD(switch, Switch);
INSTKEYWORD(indirectbr, IndirectBr);
INSTKEYWORD(invoke, Invoke);
diff --git a/llvm/lib/Bitcode/Writer/BitcodeWriter.cpp b/llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
index cc0491bd8577f..3410506530218 100644
--- a/llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
+++ b/llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
@@ -3255,19 +3255,20 @@ void ModuleBitcodeWriter::writeInstruction(const Instruction &I,
}
}
break;
- case Instruction::Br:
- {
+ case Instruction::UncondBr: {
Code = bitc::FUNC_CODE_INST_BR;
AbbrevToUse = FUNCTION_INST_BR_UNCOND_ABBREV;
- const BranchInst &II = cast<BranchInst>(I);
+ const UncondBrInst &II = cast<UncondBrInst>(I);
Vals.push_back(VE.getValueID(II.getSuccessor(0)));
- if (II.isConditional()) {
- Vals.push_back(VE.getValueID(II.getSuccessor(1)));
- pushValue(II.getCondition(), InstID, Vals);
- AbbrevToUse = FUNCTION_INST_BR_COND_ABBREV;
- }
- }
- break;
+ } break;
+ case Instruction::CondBr: {
+ Code = bitc::FUNC_CODE_INST_BR;
+ AbbrevToUse = FUNCTION_INST_BR_COND_ABBREV;
+ const CondBrInst &II = cast<CondBrInst>(I);
+ Vals.push_back(VE.getValueID(II.getSuccessor(0)));
+ Vals.push_back(VE.getValueID(II.getSuccessor(1)));
+ pushValue(II.getCondition(), InstID, Vals);
+ } break;
case Instruction::Switch:
{
Code = bitc::FUNC_CODE_INST_SWITCH;
diff --git a/llvm/lib/CodeGen/CodeGenPrepare.cpp b/llvm/lib/CodeGen/CodeGenPrepare.cpp
index 537b91bc39e0e..2f5304ebbbbad 100644
--- a/llvm/lib/CodeGen/CodeGenPrepare.cpp
+++ b/llvm/lib/CodeGen/CodeGenPrepare.cpp
@@ -8807,7 +8807,7 @@ static bool tryUnmergingGEPsAcrossIndirectBr(GetElementPtrInst *GEPI,
return true;
}
-static bool optimizeBranch(BranchInst *Branch, const TargetLowering &TLI,
+static bool optimizeBranch(CondBrInst *Branch, const TargetLowering &TLI,
SmallPtrSet<BasicBlock *, 32> &FreshBBs,
bool IsHugeFunc) {
// Try and convert
@@ -8820,7 +8820,7 @@ static bool optimizeBranch(BranchInst *Branch, const TargetLowering &TLI,
// br %c, bla, blb
// Creating the cmp to zero can be better for the backend, especially if the
// lshr produces flags that can be used automatically.
- if (!TLI.preferZeroCompareBranch() || !Branch->isConditional())
+ if (!TLI.preferZeroCompareBranch())
return false;
ICmpInst *Cmp = dyn_cast<ICmpInst>(Branch->getCondition());
@@ -9055,8 +9055,8 @@ bool CodeGenPrepare::optimizeInst(Instruction *I, ModifyDT &ModifiedDT) {
return optimizeSwitchInst(cast<SwitchInst>(I));
case Instruction::ExtractElement:
return optimizeExtractElementInst(cast<ExtractElementInst>(I));
- case Instruction::Br:
- return optimizeBranch(cast<BranchInst>(I), *TLI, FreshBBs, IsHugeFunc);
+ case Instruction::CondBr:
+ return optimizeBranch(cast<CondBrInst>(I), *TLI, FreshBBs, IsHugeFunc);
}
return AnyChange;
diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
index 56da65cf1ad54..a7603dd272a92 100644
--- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
@@ -603,22 +603,27 @@ bool IRTranslator::shouldEmitAsBranches(
return true;
}
-bool IRTranslator::translateBr(const User &U, MachineIRBuilder &MIRBuilder) {
- const BranchInst &BrInst = cast<BranchInst>(U);
+bool IRTranslator::translateUncondBr(const User &U,
+ MachineIRBuilder &MIRBuilder) {
+ const UncondBrInst &BrInst = cast<UncondBrInst>(U);
auto &CurMBB = MIRBuilder.getMBB();
auto *Succ0MBB = &getMBB(*BrInst.getSuccessor(0));
- if (BrInst.isUnconditional()) {
- // If the unconditional target is the layout successor, fallthrough.
- if (OptLevel == CodeGenOptLevel::None ||
- !CurMBB.isLayoutSuccessor(Succ0MBB))
- MIRBuilder.buildBr(*Succ0MBB);
+ // If the unconditional target is the layout successor, fallthrough.
+ if (OptLevel == CodeGenOptLevel::None || !CurMBB.isLayoutSuccessor(Succ0MBB))
+ MIRBuilder.buildBr(*Succ0MBB);
- // Link successors.
- for (const BasicBlock *Succ : successors(&BrInst))
- CurMBB.addSuccessor(&getMBB(*Succ));
- return true;
- }
+ // Link successors.
+ for (const BasicBlock *Succ : successors(&BrInst))
+ CurMBB.addSuccessor(&getMBB(*Succ));
+ return true;
+}
+
+bool IRTranslator::translateCondBr(const User &U,
+ MachineIRBuilder &MIRBuilder) {
+ const CondBrInst &BrInst = cast<CondBrInst>(U);
+ auto &CurMBB = MIRBuilder.getMBB();
+ auto *Succ0MBB = &getMBB(*BrInst.getSuccessor(0));
// If this condition is one of the special cases we handle, do special stuff
// now.
diff --git a/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp b/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
index 3247a18bde637..d4173d09ece06 100644
--- a/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
@@ -1779,19 +1779,12 @@ bool FastISel::selectOperator(const User *I, unsigned Opcode) {
case Instruction::GetElementPtr:
return selectGetElementPtr(I);
- case Instruction::Br: {
- const BranchInst *BI = cast<BranchInst>(I);
-
- if (BI->isUnconditional()) {
- const BasicBlock *LLVMSucc = BI->getSuccessor(0);
- MachineBasicBlock *MSucc = FuncInfo.getMBB(LLVMSucc);
- fastEmitBranch(MSucc, BI->getDebugLoc());
- return true;
- }
-
- // Conditional branches are not handed yet.
- // Halt "fast" selection and bail.
- return false;
+ case Instruction::UncondBr: {
+ const UncondBrInst *BI = cast<UncondBrInst>(I);
+ const BasicBlock *LLVMSucc = BI->getSuccessor(0);
+ MachineBasicBlock *MSucc = FuncInfo.getMBB(LLVMSucc);
+ fastEmitBranch(MSucc, BI->getDebugLoc());
+ return true;
}
case Instruction::Unreachable: {
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index e21bfa8498c88..89a314444b0f5 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -2802,29 +2802,34 @@ SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases) {
return true;
}
-void SelectionDAGBuilder::visitBr(const BranchInst &I) {
+void SelectionDAGBuilder::visitUncondBr(const UncondBrInst &I) {
MachineBasicBlock *BrMBB = FuncInfo.MBB;
// Update machine-CFG edges.
MachineBasicBlock *Succ0MBB = FuncInfo.getMBB(I.getSuccessor(0));
- if (I.isUnconditional()) {
- // Update machine-CFG edges.
- BrMBB->addSuccessor(Succ0MBB);
-
- // If this is not a fall-through branch or optimizations are switched off,
- // emit the branch.
- if (Succ0MBB != NextBlock(BrMBB) ||
- TM.getOptLevel() == CodeGenOptLevel::None) {
- auto Br = DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other,
- getControlRoot(), DAG.getBasicBlock(Succ0MBB));
- setValue(&I, Br);
- DAG.setRoot(Br);
- }
+ // Update machine-CFG edges.
+ BrMBB->addSuccessor(Succ0MBB);
- return;
+ // If this is not a fall-through branch or optimizations are switched off,
+ // emit the branch.
+ if (Succ0MBB != NextBlock(BrMBB) ||
+ TM.getOptLevel() == CodeGenOptLevel::None) {
+ auto Br = DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, getControlRoot(),
+ DAG.getBasicBlock(Succ0MBB));
+ setValue(&I, Br);
+ DAG.setRoot(Br);
}
+ return;
+}
+
+void SelectionDAGBuilder::visitCondBr(const CondBrInst &I) {
+ MachineBasicBlock *BrMBB = FuncInfo.MBB;
+
+ // Update machine-CFG edges.
+ MachineBasicBlock *Succ0MBB = FuncInfo.getMBB(I.getSuccessor(0));
+
// If this condition is one of the special cases we handle, do special stuff
// now.
const Value *CondVal = I.getCondition();
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
index f8aecea25b3d6..c6efbaee44791 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
@@ -522,7 +522,8 @@ class SelectionDAGBuilder {
private:
// Terminator instructions.
void visitRet(const ReturnInst &I);
- void visitBr(const BranchInst &I);
+ void visitUncondBr(const UncondBrInst &I);
+ void visitCondBr(const CondBrInst &I);
void visitSwitch(const SwitchInst &I);
void visitIndirectBr(const IndirectBrInst &I);
void visitUnreachable(const UnreachableInst &I);
diff --git a/llvm/lib/CodeGen/TargetLoweringBase.cpp b/llvm/lib/CodeGen/TargetLoweringBase.cpp
index 17737a59bd768..96111f5eb687c 100644
--- a/llvm/lib/CodeGen/TargetLoweringBase.cpp
+++ b/llvm/lib/CodeGen/TargetLoweringBase.cpp
@@ -2167,7 +2167,8 @@ int TargetLoweringBase::InstructionOpcodeToISD(unsigned Opcode) const {
};
switch (static_cast<InstructionOpcodes>(Opcode)) {
case Ret: return 0;
- case Br: return 0;
+ case UncondBr: return 0;
+ case CondBr: return 0;
case Switch: return 0;
case IndirectBr: return 0;
case Invoke: return 0;
diff --git a/llvm/lib/CodeGen/TypePromotion.cpp b/llvm/lib/CodeGen/TypePromotion.cpp
index 0865597dadcd6..a6014ca851fae 100644
--- a/llvm/lib/CodeGen/TypePromotion.cpp
+++ b/llvm/lib/CodeGen/TypePromotion.cpp
@@ -732,7 +732,8 @@ bool TypePromotionImpl::isSupportedValue(Value *V) {
!GenerateSignBits(I);
case Instruction::GetElementPtr:
case Instruction::Store:
- case Instruction::Br:
+ case Instruction::UncondBr:
+ case Instruction::CondBr:
case Instruction::Switch:
return true;
case Instruction::PHI:
diff --git a/llvm/lib/FuzzMutate/RandomIRBuilder.cpp b/llvm/lib/FuzzMutate/RandomIRBuilder.cpp
index 8b034137e4702..4e4732ae08c1b 100644
--- a/llvm/lib/FuzzMutate/RandomIRBuilder.cpp
+++ b/llvm/lib/FuzzMutate/RandomIRBuilder.cpp
@@ -314,7 +314,7 @@ static bool isCompatibleReplacement(const Instruction *I, const Use &Operand,
// Modify other operands, like switch case may accidently change case from
// ConstantInt to a register, which is illegal.
case Instruction::Switch:
- case Instruction::Br:
+ case Instruction::CondBr:
if (OperandNo >= 1)
return false;
break;
diff --git a/llvm/lib/IR/Instruction.cpp b/llvm/lib/IR/Instruction.cpp
index 67fad4028df5f..e324528298532 100644
--- a/llvm/lib/IR/Instruction.cpp
+++ b/llvm/lib/IR/Instruction.cpp
@@ -797,7 +797,8 @@ const char *Instruction::getOpcodeName(unsigned OpCode) {
switch (OpCode) {
// Terminators
case Ret: return "ret";
- case Br: return "br";
+ case UncondBr: return "br";
+ case CondBr: return "br";
case Switch: return "switch";
case IndirectBr: return "indirectbr";
case Invoke: return "invoke";
diff --git a/llvm/lib/IR/Instructions.cpp b/llvm/lib/IR/Instructions.cpp
index 52b6c35e18d95..3c3b8e1d3637c 100644
--- a/llvm/lib/IR/Instructions.cpp
+++ b/llvm/lib/IR/Instructions.cpp
@@ -1186,27 +1186,39 @@ UnreachableInst::UnreachableInst(LLVMContext &Context,
AllocMarker, InsertBefore) {}
//===----------------------------------------------------------------------===//
-// BranchInst Implementation
+// UncondBrInst Implementation
//===----------------------------------------------------------------------===//
-void BranchInst::AssertOK() {
- if (isConditional())
- assert(getCondition()->getType()->isIntegerTy(1) &&
- "May only branch on boolean predicates!");
-}
-
-BranchInst::BranchInst(BasicBlock *IfTrue, AllocInfo AllocInfo,
- InsertPosition InsertBefore)
- : Instruction(Type::getVoidTy(IfTrue->getContext()), Instruction::Br,
- AllocInfo, InsertBefore) {
+UncondBrInst::UncondBrInst(BasicBlock *IfTrue, AllocInfo AllocInfo,
+ InsertPosition InsertBefore)
+ : BranchInst(Type::getVoidTy(IfTrue->getContext()), Instruction::UncondBr,
+ AllocInfo, InsertBefore) {
assert(IfTrue && "Branch destination may not be null!");
Op<-1>() = IfTrue;
}
-BranchInst::BranchInst(BasicBlock *IfTrue, BasicBlock *IfFalse, Value *Cond,
+UncondBrInst::UncondBrInst(const UncondBrInst &BI, AllocInfo AllocInfo)
+ : BranchInst(Type::getVoidTy(BI.getContext()), Instruction::UncondBr,
+ AllocInfo) {
+ assert(getNumOperands() == BI.getNumOperands() &&
+ "Wrong number of operands allocated");
+ Op<-1>() = BI.Op<-1>();
+ SubclassOptionalData = BI.SubclassOptionalData;
+}
+
+//===----------------------------------------------------------------------===//
+// CondBrInst Implementation
+//===----------------------------------------------------------------------===//
+
+void CondBrInst::AssertOK() {
+ assert(getCondition()->getType()->isIntegerTy(1) &&
+ "May only branch on boolean predicates!");
+}
+
+CondBrInst::CondBrInst(BasicBlock *IfTrue, BasicBlock *IfFalse, Value *Cond,
AllocInfo AllocInfo, InsertPosition InsertBefore)
- : Instruction(Type::getVoidTy(IfTrue->getContext()), Instruction::Br,
- AllocInfo, InsertBefore) {
+ : BranchInst(Type::getVoidTy(IfTrue->getContext()), Instruction::CondBr,
+ AllocInfo, InsertBefore) {
// Assign in order of operand index to make use-list order predictable.
Op<-3>() = Cond;
Op<-2>() = IfFalse;
@@ -1216,24 +1228,19 @@ BranchInst::BranchInst(BasicBlock *IfTrue, BasicBlock *IfFalse, Value *Cond,
#endif
}
-BranchInst::BranchInst(const BranchInst &BI, AllocInfo AllocInfo)
- : Instruction(Type::getVoidTy(BI.getContext()), Instruction::Br,
- AllocInfo) {
+CondBrInst::CondBrInst(const CondBrInst &BI, AllocInfo AllocInfo)
+ : BranchInst(Type::getVoidTy(BI.getContext()), Instruction::CondBr,
+ AllocInfo) {
assert(getNumOperands() == BI.getNumOperands() &&
"Wrong number of operands allocated");
// Assign in order of operand index to make use-list order predictable.
- if (BI.getNumOperands() != 1) {
- assert(BI.getNumOperands() == 3 && "BR can have 1 or 3 operands!");
- Op<-3>() = BI.Op<-3>();
- Op<-2>() = BI.Op<-2>();
- }
+ Op<-3>() = BI.Op<-3>();
+ Op<-2>() = BI.Op<-2>();
Op<-1>() = BI.Op<-1>();
SubclassOptionalData = BI.SubclassOptionalData;
}
-void BranchInst::swapSuccessors() {
- assert(isConditional() &&
- "Cannot swap successors of an unconditional branch");
+void CondBrInst::swapSuccessors() {
Op<-1>().swap(Op<-2>());
// Update profile metadata if present and it matches our structural
@@ -4499,9 +4506,14 @@ ReturnInst *ReturnInst::cloneImpl() const {
return new (AllocMarker) ReturnInst(*this, AllocMarker);
}
-BranchInst *BranchInst::cloneImpl() const {
+UncondBrInst *UncondBrInst::cloneImpl() const {
+ IntrusiveOperandsAllocMarker AllocMarker{getNumOperands()};
+ return new (AllocMarker) UncondBrInst(*this, AllocMarker);
+}
+
+CondBrInst *CondBrInst::cloneImpl() const {
IntrusiveOperandsAllocMarker AllocMarker{getNumOperands()};
- return new (AllocMarker) BranchInst(*this, AllocMarker);
+ return new (AllocMarker) CondBrInst(*this, AllocMarker);
}
SwitchInst *SwitchInst::cloneImpl() const { return new SwitchInst(*this); }
diff --git a/llvm/lib/IR/Metadata.cpp b/llvm/lib/IR/Metadata.cpp
index 7f1b9b4d64d56..27aaecde6d199 100644
--- a/llvm/lib/IR/Metadata.cpp
+++ b/llvm/lib/IR/Metadata.cpp
@@ -1236,7 +1236,7 @@ MDNode *MDNode::getMergedProfMetadata(MDNode *A, MDNode *B,
auto IsLegal = [](const Instruction &I) -> bool {
switch (I.getOpcode()) {
case Instruction::Invoke:
- case Instruction::Br:
+ case Instruction::CondBr:
case Instruction::Switch:
case Instruction::Call:
case Instruction::IndirectBr:
@@ -1889,12 +1889,13 @@ void Instruction::getAllMetadataImpl(
}
bool Instruction::extractProfTotalWeight(uint64_t &TotalVal) const {
- assert(
- (getOpcode() == Instruction::Br || getOpcode() == Instruction::Select ||
- getOpcode() == Instruction::Call || getOpcode() == Instruction::Invoke ||
- getOpcode() == Instruction::IndirectBr ||
- getOpcode() == Instruction::Switch) &&
- "Looking for branch weights on something besides branch");
+ assert((getOpcode() == Instruction::CondBr ||
+ getOpcode() == Instruction::Select ||
+ getOpcode() == Instruction::Call ||
+ getOpcode() == Instruction::Invoke ||
+ getOpcode() == Instruction::IndirectBr ||
+ getOpcode() == Instruction::Switch) &&
+ "Looking for branch weights on something besides branch");
return ::extractProfTotalWeight(*this, TotalVal);
}
diff --git a/llvm/lib/IR/ProfDataUtils.cpp b/llvm/lib/IR/ProfDataUtils.cpp
index 00410a74f20a9..80eb7506cfab5 100644
--- a/llvm/lib/IR/ProfDataUtils.cpp
+++ b/llvm/lib/IR/ProfDataUtils.cpp
@@ -217,8 +217,7 @@ bool llvm::extractBranchWeights(const Instruction &I,
bool llvm::extractBranchWeights(const Instruction &I, uint64_t &TrueVal,
uint64_t &FalseVal) {
- assert((I.getOpcode() == Instruction::Br ||
- I.getOpcode() == Instruction::Select) &&
+ assert((isa<BranchInst, SelectInst>(I)) &&
"Looking for branch weights on something besides branch, select, or "
"switch");
diff --git a/llvm/lib/SandboxIR/Context.cpp b/llvm/lib/SandboxIR/Context.cpp
index c0d207af30a3a..04d9f6de83685 100644
--- a/llvm/lib/SandboxIR/Context.cpp
+++ b/llvm/lib/SandboxIR/Context.cpp
@@ -113,7 +113,8 @@ Value *Context::getOrCreateValueInternal(llvm::Value *LLVMV, llvm::User *U) {
std::unique_ptr<InsertValueInst>(new InsertValueInst(LLVMIns, *this));
return It->second.get();
}
- case llvm::Instruction::Br: {
+ case llvm::Instruction::UncondBr:
+ case llvm::Instruction::CondBr: {
auto *LLVMBr = cast<llvm::BranchInst>(LLVMV);
It->second = std::unique_ptr<BranchInst>(new BranchInst(LLVMBr, *this));
return It->second.get();
diff --git a/llvm/lib/Target/AArch64/AArch64FastISel.cpp b/llvm/lib/Target/AArch64/AArch64FastISel.cpp
index 8c0377fa5550f..5f6cee43930ac 100644
--- a/llvm/lib/Target/AArch64/AArch64FastISel.cpp
+++ b/llvm/lib/Target/AArch64/AArch64FastISel.cpp
@@ -5128,7 +5128,7 @@ bool AArch64FastISel::fastSelectInstruction(const Instruction *I) {
case Instruction::Or:
case Instruction::Xor:
return selectLogicalOp(I);
- case Instruction::Br:
+ case Instruction::CondBr:
return selectBranch(I);
case Instruction::IndirectBr:
return selectIndirectBr(I);
diff --git a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
index b96d251a9c4d9..d663d7253256e 100644
--- a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
@@ -6798,11 +6798,10 @@ bool AArch64TTIImpl::isProfitableToSinkOperands(
Ops.push_back(&I->getOperandUse(0));
return true;
}
- case Instruction::Br: {
- if (cast<BranchInst>(I)->isUnconditional())
- return false;
-
- if (!ShouldSinkCondition(cast<BranchInst>(I)->getCondition(), Ops))
+ case Instruction::UncondBr:
+ return false;
+ case Instruction::CondBr: {
+ if (!ShouldSinkCondition(cast<CondBrInst>(I)->getCondition(), Ops))
return false;
Ops.push_back(&I->getOperandUse(0));
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
index 6eca575cd180f..4804392e8ae46 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
@@ -852,15 +852,13 @@ InstructionCost GCNTTIImpl::getCFInstrCost(unsigned Opcode,
(CostKind == TTI::TCK_CodeSize || CostKind == TTI::TCK_SizeAndLatency);
const int CBrCost = SCost ? 5 : 7;
switch (Opcode) {
- case Instruction::Br: {
+ case Instruction::UncondBr:
// Branch instruction takes about 4 slots on gfx900.
- const auto *BI = dyn_cast_or_null<BranchInst>(I);
- if (BI && BI->isUnconditional())
- return SCost ? 1 : 4;
+ return SCost ? 1 : 4;
+ case Instruction::CondBr:
// Suppose conditional branch takes additional 3 exec manipulations
// instructions in average.
return CBrCost;
- }
case Instruction::Switch: {
const auto *SI = dyn_cast_or_null<SwitchInst>(I);
// Each case (including default) takes 1 cmp + 1 cbr instructions in
diff --git a/llvm/lib/Target/AMDGPU/R600TargetTransformInfo.cpp b/llvm/lib/Target/AMDGPU/R600TargetTransformInfo.cpp
index c08edc1bb5512..1ab15b13d7698 100644
--- a/llvm/lib/Target/AMDGPU/R600TargetTransformInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/R600TargetTransformInfo.cpp
@@ -100,7 +100,8 @@ InstructionCost R600TTIImpl::getCFInstrCost(unsigned Opcode,
// XXX - For some reason this isn't called for switch.
switch (Opcode) {
- case Instruction::Br:
+ case Instruction::UncondBr:
+ case Instruction::CondBr:
case Instruction::Ret:
return 10;
default:
diff --git a/llvm/lib/Target/ARM/ARMFastISel.cpp b/llvm/lib/Target/ARM/ARMFastISel.cpp
index 80eb0f5f810ff..c24421ce6b658 100644
--- a/llvm/lib/Target/ARM/ARMFastISel.cpp
+++ b/llvm/lib/Target/ARM/ARMFastISel.cpp
@@ -2911,7 +2911,7 @@ bool ARMFastISel::fastSelectInstruction(const Instruction *I) {
return SelectLoad(I);
case Instruction::Store:
return SelectStore(I);
- case Instruction::Br:
+ case Instruction::CondBr:
return SelectBranch(I);
case Instruction::IndirectBr:
return SelectIndirectBr(I);
diff --git a/llvm/lib/Target/Mips/MipsFastISel.cpp b/llvm/lib/Target/Mips/MipsFastISel.cpp
index cd763e2748995..be866c67932c0 100644
--- a/llvm/lib/Target/Mips/MipsFastISel.cpp
+++ b/llvm/lib/Target/Mips/MipsFastISel.cpp
@@ -2079,7 +2079,7 @@ bool MipsFastISel::fastSelectInstruction(const Instruction *I) {
case Instruction::Or:
case Instruction::Xor:
return selectLogicalOp(I);
- case Instruction::Br:
+ case Instruction::CondBr:
return selectBranch(I);
case Instruction::Ret:
return selectRet(I);
diff --git a/llvm/lib/Target/PowerPC/PPCFastISel.cpp b/llvm/lib/Target/PowerPC/PPCFastISel.cpp
index 6a858666bfda6..28e6680043e07 100644
--- a/llvm/lib/Target/PowerPC/PPCFastISel.cpp
+++ b/llvm/lib/Target/PowerPC/PPCFastISel.cpp
@@ -1938,7 +1938,7 @@ bool PPCFastISel::fastSelectInstruction(const Instruction *I) {
return SelectLoad(I);
case Instruction::Store:
return SelectStore(I);
- case Instruction::Br:
+ case Instruction::CondBr:
return SelectBranch(I);
case Instruction::IndirectBr:
return SelectIndirectBr(I);
diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
index ffb64d9f52beb..39181237459d0 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -1985,7 +1985,7 @@ RISCVTTIImpl::getMinMaxReductionCost(Intrinsic::ID IID, VectorType *Ty,
ExtraCost = 1 +
getCastInstrCost(Instruction::UIToFP, DstTy, SrcTy,
TTI::CastContextHint::None, CostKind) +
- getCFInstrCost(Instruction::Br, CostKind);
+ getCFInstrCost(Instruction::CondBr, CostKind);
}
break;
@@ -2004,7 +2004,7 @@ RISCVTTIImpl::getMinMaxReductionCost(Intrinsic::ID IID, VectorType *Ty,
ExtraCost = 1 +
getCastInstrCost(Instruction::UIToFP, DstTy, SrcTy,
TTI::CastContextHint::None, CostKind) +
- getCFInstrCost(Instruction::Br, CostKind);
+ getCFInstrCost(Instruction::CondBr, CostKind);
}
break;
}
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp
index c869164d96945..77fb222eb74a4 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp
@@ -1502,7 +1502,7 @@ bool WebAssemblyFastISel::fastSelectInstruction(const Instruction *I) {
return selectLoad(I);
case Instruction::Store:
return selectStore(I);
- case Instruction::Br:
+ case Instruction::CondBr:
return selectBr(I);
case Instruction::Ret:
return selectRet(I);
diff --git a/llvm/lib/Target/X86/X86FastISel.cpp b/llvm/lib/Target/X86/X86FastISel.cpp
index bd36f2ccf4aed..8e5f22ec0cb50 100644
--- a/llvm/lib/Target/X86/X86FastISel.cpp
+++ b/llvm/lib/Target/X86/X86FastISel.cpp
@@ -3645,7 +3645,7 @@ X86FastISel::fastSelectInstruction(const Instruction *I) {
return X86SelectZExt(I);
case Instruction::SExt:
return X86SelectSExt(I);
- case Instruction::Br:
+ case Instruction::CondBr:
return X86SelectBranch(I);
case Instruction::LShr:
case Instruction::AShr:
diff --git a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
index 96541daaeef8e..cbe44de4004f3 100644
--- a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
+++ b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
@@ -5465,7 +5465,7 @@ X86TTIImpl::getMaskedMemoryOpCost(const MemIntrinsicCostAttributes &MICA,
InstructionCost ScalarCompareCost = getCmpSelInstrCost(
Instruction::ICmp, Type::getInt8Ty(SrcVTy->getContext()), nullptr,
CmpInst::BAD_ICMP_PREDICATE, CostKind);
- InstructionCost BranchCost = getCFInstrCost(Instruction::Br, CostKind);
+ InstructionCost BranchCost = getCFInstrCost(Instruction::CondBr, CostKind);
InstructionCost MaskCmpCost = NumElem * (BranchCost + ScalarCompareCost);
InstructionCost ValueSplitCost = getScalarizationOverhead(
SrcVTy, DemandedElts, IsLoad, IsStore, CostKind);
diff --git a/llvm/lib/Transforms/IPO/Attributor.cpp b/llvm/lib/Transforms/IPO/Attributor.cpp
index 9a35696b7627c..8fdadd371634e 100644
--- a/llvm/lib/Transforms/IPO/Attributor.cpp
+++ b/llvm/lib/Transforms/IPO/Attributor.cpp
@@ -3255,7 +3255,8 @@ void InformationCache::initializeInformationCache(const Function &CF,
case Instruction::CatchSwitch:
case Instruction::AtomicRMW:
case Instruction::AtomicCmpXchg:
- case Instruction::Br:
+ case Instruction::UncondBr:
+ case Instruction::CondBr:
case Instruction::Resume:
case Instruction::Ret:
case Instruction::Load:
diff --git a/llvm/lib/Transforms/IPO/AttributorAttributes.cpp b/llvm/lib/Transforms/IPO/AttributorAttributes.cpp
index b80a514b68246..b5703f7b87e74 100644
--- a/llvm/lib/Transforms/IPO/AttributorAttributes.cpp
+++ b/llvm/lib/Transforms/IPO/AttributorAttributes.cpp
@@ -3011,11 +3011,7 @@ struct AAUndefinedBehaviorImpl : public AAUndefinedBehavior {
return true;
// We know we have a branch instruction.
- auto *BrInst = cast<BranchInst>(&I);
-
- // Unconditional branches are never considered UB.
- if (BrInst->isUnconditional())
- return true;
+ auto *BrInst = cast<CondBrInst>(&I);
// Either we stopped and the appropriate action was taken,
// or we got back a simplified value to continue.
@@ -3129,7 +3125,7 @@ struct AAUndefinedBehaviorImpl : public AAUndefinedBehavior {
Instruction::AtomicRMW},
UsedAssumedInformation,
/* CheckBBLivenessOnly */ true);
- A.checkForAllInstructions(InspectBrInstForUB, *this, {Instruction::Br},
+ A.checkForAllInstructions(InspectBrInstForUB, *this, {Instruction::CondBr},
UsedAssumedInformation,
/* CheckBBLivenessOnly */ true);
A.checkForAllCallLikeInstructions(InspectCallSiteForUB, *this,
@@ -3172,13 +3168,8 @@ struct AAUndefinedBehaviorImpl : public AAUndefinedBehavior {
case Instruction::Store:
case Instruction::AtomicCmpXchg:
case Instruction::AtomicRMW:
+ case Instruction::CondBr:
return !AssumedNoUBInsts.count(I);
- case Instruction::Br: {
- auto *BrInst = cast<BranchInst>(I);
- if (BrInst->isUnconditional())
- return false;
- return !AssumedNoUBInsts.count(I);
- } break;
default:
return false;
}
@@ -4839,7 +4830,8 @@ ChangeStatus AAIsDeadFunction::updateImpl(Attributor &A) {
UsedAssumedInformation = identifyAliveSuccessors(A, cast<InvokeInst>(*I),
*this, AliveSuccessors);
break;
- case Instruction::Br:
+ case Instruction::UncondBr:
+ case Instruction::CondBr:
UsedAssumedInformation = identifyAliveSuccessors(A, cast<BranchInst>(*I),
*this, AliveSuccessors);
break;
diff --git a/llvm/lib/Transforms/IPO/IROutliner.cpp b/llvm/lib/Transforms/IPO/IROutliner.cpp
index 574e4639b5436..ef4d8eda08f13 100644
--- a/llvm/lib/Transforms/IPO/IROutliner.cpp
+++ b/llvm/lib/Transforms/IPO/IROutliner.cpp
@@ -2565,8 +2565,8 @@ static InstructionCost findCostForOutputBlocks(Module &M,
OutputCost += StoreCost * NumOutputBranches;
}
- InstructionCost BranchCost =
- TTI.getCFInstrCost(Instruction::Br, TargetTransformInfo::TCK_CodeSize);
+ InstructionCost BranchCost = TTI.getCFInstrCost(
+ Instruction::UncondBr, TargetTransformInfo::TCK_CodeSize);
LLVM_DEBUG(dbgs() << "Adding " << BranchCost << " to the current cost for"
<< " a branch instruction\n");
OutputCost += BranchCost * NumOutputBranches;
@@ -2579,8 +2579,8 @@ static InstructionCost findCostForOutputBlocks(Module &M,
Instruction::ICmp, Type::getInt32Ty(M.getContext()),
Type::getInt32Ty(M.getContext()), CmpInst::BAD_ICMP_PREDICATE,
TargetTransformInfo::TCK_CodeSize);
- InstructionCost BranchCost =
- TTI.getCFInstrCost(Instruction::Br, TargetTransformInfo::TCK_CodeSize);
+ InstructionCost BranchCost = TTI.getCFInstrCost(
+ Instruction::CondBr, TargetTransformInfo::TCK_CodeSize);
unsigned DifferentBlocks = CurrentGroup.OutputGVNCombinations.size();
InstructionCost TotalCost = ComparisonCost * BranchCost * DifferentBlocks;
diff --git a/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp b/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
index 0ca5da1bbf251..fd6d97f69e052 100644
--- a/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
@@ -1455,7 +1455,7 @@ void InstCombinerImpl::freelyInvertAllUsersOf(Value *I, Value *IgnoredUser) {
SI->swapProfMetadata();
break;
}
- case Instruction::Br: {
+ case Instruction::CondBr: {
BranchInst *BI = cast<BranchInst>(U);
BI->swapSuccessors(); // swaps prof metadata too
if (BPI)
diff --git a/llvm/lib/Transforms/Utils/BreakCriticalEdges.cpp b/llvm/lib/Transforms/Utils/BreakCriticalEdges.cpp
index 8aa8aa2c60800..78f2ab5dffa98 100644
--- a/llvm/lib/Transforms/Utils/BreakCriticalEdges.cpp
+++ b/llvm/lib/Transforms/Utils/BreakCriticalEdges.cpp
@@ -334,7 +334,8 @@ findIBRPredecessor(BasicBlock *BB, SmallVectorImpl<BasicBlock *> &OtherPreds) {
return nullptr;
IBB = PredBB;
break;
- case Instruction::Br:
+ case Instruction::UncondBr:
+ case Instruction::CondBr:
case Instruction::Switch:
OtherPreds.push_back(PredBB);
continue;
diff --git a/llvm/lib/Transforms/Utils/InlineFunction.cpp b/llvm/lib/Transforms/Utils/InlineFunction.cpp
index 3230b306f17d1..a779a25f7378e 100644
--- a/llvm/lib/Transforms/Utils/InlineFunction.cpp
+++ b/llvm/lib/Transforms/Utils/InlineFunction.cpp
@@ -3302,7 +3302,7 @@ void llvm::InlineFunctionImpl(CallBase &CB, InlineFunctionInfo &IFI,
// basic block of the inlined function.
//
Instruction *Br = OrigBB->getTerminator();
- assert(Br && Br->getOpcode() == Instruction::Br &&
+ assert(Br && Br->getOpcode() == Instruction::UncondBr &&
"splitBasicBlock broken!");
Br->setOperand(0, &*FirstNewBlock);
diff --git a/llvm/lib/Transforms/Utils/SimplifyCFG.cpp b/llvm/lib/Transforms/Utils/SimplifyCFG.cpp
index 65a8953919aed..e104fd563c331 100644
--- a/llvm/lib/Transforms/Utils/SimplifyCFG.cpp
+++ b/llvm/lib/Transforms/Utils/SimplifyCFG.cpp
@@ -295,7 +295,6 @@ class SimplifyCFGOpt {
bool simplifySwitch(SwitchInst *SI, IRBuilder<> &Builder);
bool simplifyDuplicateSwitchArms(SwitchInst *SI, DomTreeUpdater *DTU);
bool simplifyIndirectBr(IndirectBrInst *IBI);
- bool simplifyBranch(BranchInst *Branch, IRBuilder<> &Builder);
bool simplifyUncondBranch(BranchInst *BI, IRBuilder<> &Builder);
bool simplifyCondBranch(BranchInst *BI, IRBuilder<> &Builder);
bool foldCondBranchOnValueKnownInPredecessor(BranchInst *BI);
@@ -8370,11 +8369,6 @@ static bool tryToMergeLandingPad(LandingPadInst *LPad, BranchInst *BI,
return false;
}
-bool SimplifyCFGOpt::simplifyBranch(BranchInst *Branch, IRBuilder<> &Builder) {
- return Branch->isUnconditional() ? simplifyUncondBranch(Branch, Builder)
- : simplifyCondBranch(Branch, Builder);
-}
-
bool SimplifyCFGOpt::simplifyUncondBranch(BranchInst *BI,
IRBuilder<> &Builder) {
BasicBlock *BB = BI->getParent();
@@ -8933,8 +8927,11 @@ bool SimplifyCFGOpt::simplifyOnce(BasicBlock *BB) {
Instruction *Terminator = BB->getTerminator();
Builder.SetInsertPoint(Terminator);
switch (Terminator->getOpcode()) {
- case Instruction::Br:
- Changed |= simplifyBranch(cast<BranchInst>(Terminator), Builder);
+ case Instruction::UncondBr:
+ Changed |= simplifyUncondBranch(cast<UncondBrInst>(Terminator), Builder);
+ break;
+ case Instruction::CondBr:
+ Changed |= simplifyCondBranch(cast<CondBrInst>(Terminator), Builder);
break;
case Instruction::Resume:
Changed |= simplifyResume(cast<ResumeInst>(Terminator), Builder);
diff --git a/llvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp b/llvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp
index fec32762db55f..12ec374867dbe 100644
--- a/llvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp
+++ b/llvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp
@@ -1795,7 +1795,8 @@ bool LoopVectorizationLegality::isVectorizableEarlyExitLoop() {
case Instruction::Load:
case Instruction::Store:
case Instruction::PHI:
- case Instruction::Br:
+ case Instruction::UncondBr:
+ case Instruction::CondBr:
// These are checked separately.
return true;
default:
diff --git a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
index 0debab4a2a0ee..2204ecdcfc59a 100644
--- a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+++ b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
@@ -5308,7 +5308,7 @@ LoopVectorizationCostModel::getMemInstScalarizationCost(Instruction *I,
Cost += TTI.getScalarizationOverhead(
VecI1Ty, APInt::getAllOnes(VF.getFixedValue()),
/*Insert=*/false, /*Extract=*/true, CostKind);
- Cost += TTI.getCFInstrCost(Instruction::Br, CostKind);
+ Cost += TTI.getCFInstrCost(Instruction::CondBr, CostKind);
if (useEmulatedMaskMemRefHack(I, VF))
// Artificially setting to a high enough value to practically disable
@@ -6169,7 +6169,8 @@ LoopVectorizationCostModel::getInstructionCost(Instruction *I,
// is scalarized or not. Therefore, we handle GEPs with the memory
// instruction cost.
return 0;
- case Instruction::Br: {
+ case Instruction::UncondBr:
+ case Instruction::CondBr: {
// In cases of scalarized and predicated instructions, there will be VF
// predicated blocks in the vectorized loop. Each branch around these
// blocks requires also an extract of its vector compare i1 element.
@@ -6191,16 +6192,16 @@ LoopVectorizationCostModel::getInstructionCost(Instruction *I,
// Return cost for branches around scalarized and predicated blocks.
auto *VecI1Ty =
VectorType::get(IntegerType::getInt1Ty(RetTy->getContext()), VF);
- return (
- TTI.getScalarizationOverhead(
- VecI1Ty, APInt::getAllOnes(VF.getFixedValue()),
- /*Insert*/ false, /*Extract*/ true, CostKind) +
- (TTI.getCFInstrCost(Instruction::Br, CostKind) * VF.getFixedValue()));
+ return (TTI.getScalarizationOverhead(
+ VecI1Ty, APInt::getAllOnes(VF.getFixedValue()),
+ /*Insert*/ false, /*Extract*/ true, CostKind) +
+ (TTI.getCFInstrCost(Instruction::CondBr, CostKind) *
+ VF.getFixedValue()));
}
if (I->getParent() == TheLoop->getLoopLatch() || VF.isScalar())
// The back-edge branch will remain, as will all scalar branches.
- return TTI.getCFInstrCost(Instruction::Br, CostKind);
+ return TTI.getCFInstrCost(Instruction::UncondBr, CostKind);
// This branch will be eliminated by if-conversion.
return 0;
diff --git a/llvm/lib/Transforms/Vectorize/VPlan.cpp b/llvm/lib/Transforms/Vectorize/VPlan.cpp
index f233f0dc1b025..0e2855dc682fb 100644
--- a/llvm/lib/Transforms/Vectorize/VPlan.cpp
+++ b/llvm/lib/Transforms/Vectorize/VPlan.cpp
@@ -810,7 +810,7 @@ InstructionCost VPRegionBlock::cost(ElementCount VF, VPCostContext &Ctx) {
InstructionCost BackedgeCost =
ForceTargetInstructionCost.getNumOccurrences()
? InstructionCost(ForceTargetInstructionCost.getNumOccurrences())
- : Ctx.TTI.getCFInstrCost(Instruction::Br, Ctx.CostKind);
+ : Ctx.TTI.getCFInstrCost(Instruction::UncondBr, Ctx.CostKind);
LLVM_DEBUG(dbgs() << "Cost of " << BackedgeCost << " for VF " << VF
<< ": vector loop backedge\n");
Cost += BackedgeCost;
diff --git a/llvm/lib/Transforms/Vectorize/VPlan.h b/llvm/lib/Transforms/Vectorize/VPlan.h
index df66dd6cee59a..b4543ba1d46e9 100644
--- a/llvm/lib/Transforms/Vectorize/VPlan.h
+++ b/llvm/lib/Transforms/Vectorize/VPlan.h
@@ -1351,7 +1351,8 @@ class LLVM_ABI_FOR_TEST VPInstruction : public VPRecipeWithIRFlags,
// Conservatively return calls have results for now.
switch (getOpcode()) {
case Instruction::Ret:
- case Instruction::Br:
+ case Instruction::UncondBr:
+ case Instruction::CondBr:
case Instruction::Store:
case Instruction::Switch:
case Instruction::IndirectBr:
diff --git a/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp b/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
index a61b9d71183a0..cd65c43682e18 100644
--- a/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
+++ b/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
@@ -2284,7 +2284,8 @@ void VPWidenRecipe::execute(VPTransformState &State) {
auto &Builder = State.Builder;
switch (Opcode) {
case Instruction::Call:
- case Instruction::Br:
+ case Instruction::UncondBr:
+ case Instruction::CondBr:
case Instruction::PHI:
case Instruction::GetElementPtr:
llvm_unreachable("This instruction is handled by a different recipe.");
@@ -3566,7 +3567,7 @@ InstructionCost VPReplicateRecipe::computeCost(ElementCount VF,
if (!PtrSCEV || Ctx.PSE.getSE()->isLoopInvariant(PtrSCEV, Ctx.L))
break;
Cost /= Ctx.getPredBlockCostDivisor(UI->getParent());
- Cost += Ctx.TTI.getCFInstrCost(Instruction::Br, Ctx.CostKind);
+ Cost += Ctx.TTI.getCFInstrCost(Instruction::CondBr, Ctx.CostKind);
auto *VecI1Ty = VectorType::get(
IntegerType::getInt1Ty(Ctx.L->getHeader()->getContext()), VF);
diff --git a/llvm/test/Analysis/IR2Vec/Inputs/dummy_2D_vocab.json b/llvm/test/Analysis/IR2Vec/Inputs/dummy_2D_vocab.json
index ae36ff54686c5..43fa573db68af 100644
--- a/llvm/test/Analysis/IR2Vec/Inputs/dummy_2D_vocab.json
+++ b/llvm/test/Analysis/IR2Vec/Inputs/dummy_2D_vocab.json
@@ -1,7 +1,8 @@
{
"Opcodes": {
"Ret": [1, 2],
- "Br": [3, 4],
+ "UncondBr": [3, 4],
+ "CondBr": [3, 4],
"Switch": [5, 6],
"IndirectBr": [7, 8],
"Invoke": [9, 10],
diff --git a/llvm/test/Analysis/IR2Vec/Inputs/dummy_3D_nonzero_arg_vocab.json b/llvm/test/Analysis/IR2Vec/Inputs/dummy_3D_nonzero_arg_vocab.json
index 9003dc73954aa..aff4ddfa5edee 100644
--- a/llvm/test/Analysis/IR2Vec/Inputs/dummy_3D_nonzero_arg_vocab.json
+++ b/llvm/test/Analysis/IR2Vec/Inputs/dummy_3D_nonzero_arg_vocab.json
@@ -1,7 +1,8 @@
{
"Opcodes": {
"Ret": [0, 0, 0],
- "Br": [0, 0, 0],
+ "UncondBr": [0, 0, 0],
+ "CondBr": [0, 0, 0],
"Switch": [0, 0, 0],
"IndirectBr": [0, 0, 0],
"Invoke": [0, 0, 0],
diff --git a/llvm/test/Analysis/IR2Vec/Inputs/dummy_3D_nonzero_opc_vocab.json b/llvm/test/Analysis/IR2Vec/Inputs/dummy_3D_nonzero_opc_vocab.json
index 7ef85490b27df..270b21295b08d 100644
--- a/llvm/test/Analysis/IR2Vec/Inputs/dummy_3D_nonzero_opc_vocab.json
+++ b/llvm/test/Analysis/IR2Vec/Inputs/dummy_3D_nonzero_opc_vocab.json
@@ -1,7 +1,8 @@
{
"Opcodes": {
"Ret": [1, 2, 3],
- "Br": [4, 5, 6],
+ "UncondBr": [4, 5, 6],
+ "CondBr": [4, 5, 6],
"Switch": [7, 8, 9],
"IndirectBr": [10, 11, 12],
"Invoke": [13, 14, 15],
diff --git a/llvm/test/Analysis/IR2Vec/Inputs/dummy_3D_nonzero_type_vocab.json b/llvm/test/Analysis/IR2Vec/Inputs/dummy_3D_nonzero_type_vocab.json
index fcc1344ada314..99e6fb2b6b72b 100644
--- a/llvm/test/Analysis/IR2Vec/Inputs/dummy_3D_nonzero_type_vocab.json
+++ b/llvm/test/Analysis/IR2Vec/Inputs/dummy_3D_nonzero_type_vocab.json
@@ -1,7 +1,8 @@
{
"Opcodes": {
"Ret": [0, 0, 0],
- "Br": [0, 0, 0],
+ "UncondBr": [0, 0, 0],
+ "CondBr": [0, 0, 0],
"Switch": [0, 0, 0],
"IndirectBr": [0, 0, 0],
"Invoke": [0, 0, 0],
diff --git a/llvm/test/Analysis/IR2Vec/Inputs/reference_default_vocab_print.txt b/llvm/test/Analysis/IR2Vec/Inputs/reference_default_vocab_print.txt
index d62b0dd157b0b..a5c1c8e209bf2 100644
--- a/llvm/test/Analysis/IR2Vec/Inputs/reference_default_vocab_print.txt
+++ b/llvm/test/Analysis/IR2Vec/Inputs/reference_default_vocab_print.txt
@@ -1,5 +1,6 @@
Key: Ret: [ 1.00 2.00 ]
-Key: Br: [ 3.00 4.00 ]
+Key: UncondBr: [ 3.00 4.00 ]
+Key: CondBr: [ 3.00 4.00 ]
Key: Switch: [ 5.00 6.00 ]
Key: IndirectBr: [ 7.00 8.00 ]
Key: Invoke: [ 9.00 10.00 ]
diff --git a/llvm/test/Analysis/IR2Vec/Inputs/reference_wtd1_vocab_print.txt b/llvm/test/Analysis/IR2Vec/Inputs/reference_wtd1_vocab_print.txt
index e443adb17ac78..ed761e6058210 100644
--- a/llvm/test/Analysis/IR2Vec/Inputs/reference_wtd1_vocab_print.txt
+++ b/llvm/test/Analysis/IR2Vec/Inputs/reference_wtd1_vocab_print.txt
@@ -1,5 +1,6 @@
Key: Ret: [ 0.50 1.00 ]
-Key: Br: [ 1.50 2.00 ]
+Key: UncondBr: [ 1.50 2.00 ]
+Key: CondBr: [ 1.50 2.00 ]
Key: Switch: [ 2.50 3.00 ]
Key: IndirectBr: [ 3.50 4.00 ]
Key: Invoke: [ 4.50 5.00 ]
diff --git a/llvm/test/Analysis/IR2Vec/Inputs/reference_wtd2_vocab_print.txt b/llvm/test/Analysis/IR2Vec/Inputs/reference_wtd2_vocab_print.txt
index 7fb6043552f7b..8fc27098c383b 100644
--- a/llvm/test/Analysis/IR2Vec/Inputs/reference_wtd2_vocab_print.txt
+++ b/llvm/test/Analysis/IR2Vec/Inputs/reference_wtd2_vocab_print.txt
@@ -1,5 +1,6 @@
Key: Ret: [ 0.10 0.20 ]
-Key: Br: [ 0.30 0.40 ]
+Key: UncondBr: [ 0.30 0.40 ]
+Key: CondBr: [ 0.30 0.40 ]
Key: Switch: [ 0.50 0.60 ]
Key: IndirectBr: [ 0.70 0.80 ]
Key: Invoke: [ 0.90 1.00 ]
diff --git a/llvm/test/Analysis/InstCount/instcount.ll b/llvm/test/Analysis/InstCount/instcount.ll
index 0d0ab2b0517cb..9c4d3f3d06457 100644
--- a/llvm/test/Analysis/InstCount/instcount.ll
+++ b/llvm/test/Analysis/InstCount/instcount.ll
@@ -9,7 +9,8 @@
; CHECK-DAG: 10 instcount - Largest number of basic blocks in a single function
; CHECK-DAG: 18 instcount - Largest number of instructions in a single function
-; CHECK-DAG: 8 instcount - Number of Br insts
+; CHECK-DAG: 6 instcount - Number of UncondBr insts
+; CHECK-DAG: 2 instcount - Number of CondBr insts
; CHECK-DAG: 6 instcount - Number of Call insts
; CHECK-DAG: 2 instcount - Number of ICmp insts
; CHECK-DAG: 2 instcount - Number of Ret insts
diff --git a/llvm/test/Transforms/IRNormalizer/naming-args-instr-blocks.ll b/llvm/test/Transforms/IRNormalizer/naming-args-instr-blocks.ll
index 7845a22e3ae17..13c83a2ebaeea 100644
--- a/llvm/test/Transforms/IRNormalizer/naming-args-instr-blocks.ll
+++ b/llvm/test/Transforms/IRNormalizer/naming-args-instr-blocks.ll
@@ -5,9 +5,9 @@ define i32 @foo(i32) {
; CHECK-LABEL: define i32 @foo(
; CHECK-SAME: i32 [[A0:%.*]]) {
; CHECK-NEXT: [[BB17254:.*:]]
-; CHECK-NEXT: %"vl24903([[A0]], 2)" = add i32 [[A0]], 2
-; CHECK-NEXT: %"op10412(vl24903)" = add i32 6, %"vl24903([[A0]], 2)"
-; CHECK-NEXT: ret i32 %"op10412(vl24903)"
+; CHECK-NEXT: %"vl72525([[A0]], 2)" = add i32 [[A0]], 2
+; CHECK-NEXT: %"op11283(vl72525)" = add i32 6, %"vl72525([[A0]], 2)"
+; CHECK-NEXT: ret i32 %"op11283(vl72525)"
;
entry:
%a = add i32 %0, 2
diff --git a/llvm/test/Transforms/IRNormalizer/naming-arguments.ll b/llvm/test/Transforms/IRNormalizer/naming-arguments.ll
index a0066c97ca3db..60c19e3dbe4dc 100644
--- a/llvm/test/Transforms/IRNormalizer/naming-arguments.ll
+++ b/llvm/test/Transforms/IRNormalizer/naming-arguments.ll
@@ -5,8 +5,8 @@ define i32 @foo(i32, i32) {
; CHECK-LABEL: define i32 @foo(
; CHECK-SAME: i32 [[A0:%.*]], i32 [[A1:%.*]]) {
; CHECK-NEXT: [[BB17254:.*:]]
-; CHECK-NEXT: %"vl20416([[A0]], [[A1]])" = mul i32 [[A0]], [[A1]]
-; CHECK-NEXT: ret i32 %"vl20416([[A0]], [[A1]])"
+; CHECK-NEXT: %"vl11241([[A0]], [[A1]])" = mul i32 [[A0]], [[A1]]
+; CHECK-NEXT: ret i32 %"vl11241([[A0]], [[A1]])"
;
%tmp = mul i32 %0, %1
ret i32 %tmp
diff --git a/llvm/test/Transforms/IRNormalizer/naming.ll b/llvm/test/Transforms/IRNormalizer/naming.ll
index 7c93a6213a4a9..9c4a402800ad3 100644
--- a/llvm/test/Transforms/IRNormalizer/naming.ll
+++ b/llvm/test/Transforms/IRNormalizer/naming.ll
@@ -5,8 +5,8 @@ define i32 @foo(i32 %a0) {
; CHECK-LABEL: define i32 @foo(
; CHECK-SAME: i32 [[A0:%.*]]) {
; CHECK-NEXT: [[BB17254:.*:]]
-; CHECK-NEXT: %"vl12603([[A0]], 2)" = add i32 [[A0]], 2
-; CHECK-NEXT: ret i32 %"vl12603([[A0]], 2)"
+; CHECK-NEXT: %"vl16132([[A0]], 2)" = add i32 [[A0]], 2
+; CHECK-NEXT: ret i32 %"vl16132([[A0]], 2)"
;
entry:
%a = add i32 %a0, 2
@@ -17,10 +17,10 @@ define i32 @bar(i32 %a0) {
; CHECK-LABEL: define i32 @bar(
; CHECK-SAME: i32 [[A0:%.*]]) {
; CHECK-NEXT: [[BB17254:.*:]]
-; CHECK-NEXT: %"vl76167([[A0]], 2)" = add i32 [[A0]], 2
-; CHECK-NEXT: %"op10412(vl76167)" = add i32 6, %"vl76167([[A0]], 2)"
-; CHECK-NEXT: %"op10412(op10412)" = add i32 8, %"op10412(vl76167)"
-; CHECK-NEXT: ret i32 %"op10412(op10412)"
+; CHECK-NEXT: %"vl35397([[A0]], 2)" = add i32 [[A0]], 2
+; CHECK-NEXT: %"op11283(vl35397)" = add i32 6, %"vl35397([[A0]], 2)"
+; CHECK-NEXT: %"op11283(op11283)" = add i32 8, %"op11283(vl35397)"
+; CHECK-NEXT: ret i32 %"op11283(op11283)"
;
entry:
%a = add i32 %a0, 2
diff --git a/llvm/test/Transforms/IRNormalizer/pass-parameters.ll b/llvm/test/Transforms/IRNormalizer/pass-parameters.ll
index f1bca3233dfee..1383ed2fa183f 100644
--- a/llvm/test/Transforms/IRNormalizer/pass-parameters.ll
+++ b/llvm/test/Transforms/IRNormalizer/pass-parameters.ll
@@ -11,8 +11,8 @@
; CHECK: define i32 @0(i32 %a0, i32 %a1) {
; CHECK-NEXT: bb17254:
-; CHECK-NEXT: %"vl12603(%a0, %a1)" = add i32 %a0, %a1
-; CHECK-NEXT: ret i32 %"vl12603(%a0, %a1)"
+; CHECK-NEXT: %"vl16132(%a0, %a1)" = add i32 %a0, %a1
+; CHECK-NEXT: ret i32 %"vl16132(%a0, %a1)"
; CHECK-NEXT: }
define i32 @0(i32, i32) {
%3 = add i32 %0, %1
diff --git a/llvm/test/Transforms/IRNormalizer/regression-convergence-tokens.ll b/llvm/test/Transforms/IRNormalizer/regression-convergence-tokens.ll
index 0c2db4a2862b2..2db29cdc1db2a 100644
--- a/llvm/test/Transforms/IRNormalizer/regression-convergence-tokens.ll
+++ b/llvm/test/Transforms/IRNormalizer/regression-convergence-tokens.ll
@@ -7,9 +7,9 @@ define i32 @nested(i32 %src) #0 {
; CHECK-SAME: i32 [[A0:%.*]]) #[[ATTR0:[0-9]+]] {
; CHECK-NEXT: [[BB15160:.*:]]
; CHECK-NEXT: [[T1:%.*]] = call token @llvm.experimental.convergence.entry()
-; CHECK-NEXT: %"vl14659llvm.experimental.convergence.anchor()" = call token @llvm.experimental.convergence.anchor()
-; CHECK-NEXT: %"op15516(vl14659)" = call i32 @llvm.amdgcn.readfirstlane.i32(i32 [[A0]]) [ "convergencectrl"(token %"vl14659llvm.experimental.convergence.anchor()") ]
-; CHECK-NEXT: ret i32 %"op15516(vl14659)"
+; CHECK-NEXT: %"vl55087llvm.experimental.convergence.anchor()" = call token @llvm.experimental.convergence.anchor()
+; CHECK-NEXT: %"op11958(vl55087)" = call i32 @llvm.amdgcn.readfirstlane.i32(i32 [[A0]]) [ "convergencectrl"(token %"vl55087llvm.experimental.convergence.anchor()") ]
+; CHECK-NEXT: ret i32 %"op11958(vl55087)"
;
%t1 = call token @llvm.experimental.convergence.entry()
%t2 = call token @llvm.experimental.convergence.anchor()
diff --git a/llvm/test/Transforms/IRNormalizer/regression-infinite-loop.ll b/llvm/test/Transforms/IRNormalizer/regression-infinite-loop.ll
index b9be105bcda48..01b3d8410a59c 100644
--- a/llvm/test/Transforms/IRNormalizer/regression-infinite-loop.ll
+++ b/llvm/test/Transforms/IRNormalizer/regression-infinite-loop.ll
@@ -5,97 +5,97 @@ define void @test(ptr, i32) {
; CHECK-LABEL: define void @test(
; CHECK-SAME: ptr [[A0:%.*]], i32 [[A1:%.*]]) {
; CHECK-NEXT: [[BB76951:.*]]:
-; CHECK-NEXT: %"vl72693([[A1]], 1)" = add i32 [[A1]], 1
+; CHECK-NEXT: %"vl74787([[A1]], 1)" = add i32 [[A1]], 1
; CHECK-NEXT: br label %[[BB16110:.*]]
; CHECK: [[BB16110]]:
-; CHECK-NEXT: %"op81283(op18080, vl72693)" = phi i32 [ %"op18080(op10412, op18131)", %[[BB16110]] ], [ %"vl72693([[A1]], 1)", %[[BB76951]] ]
-; CHECK-NEXT: %"op81283(op18131, vl72693)" = phi i32 [ %"op18131(op81283)70", %[[BB16110]] ], [ %"vl72693([[A1]], 1)", %[[BB76951]] ]
-; CHECK-NEXT: %"op13219(op81283)" = mul i32 %"op81283(op18080, vl72693)", undef
-; CHECK-NEXT: %"op16562(op13219)" = xor i32 -1, %"op13219(op81283)"
-; CHECK-NEXT: %"op12556(op16562, op81283)" = add i32 %"op16562(op13219)", %"op81283(op18080, vl72693)"
-; CHECK-NEXT: %"op18131(op81283)" = add i32 -1, %"op81283(op18131, vl72693)"
-; CHECK-NEXT: %"op18080(op12556, op18131)" = add i32 %"op12556(op16562, op81283)", %"op18131(op81283)"
-; CHECK-NEXT: %"op17720(op13219, op18080)" = mul i32 %"op13219(op81283)", %"op18080(op12556, op18131)"
-; CHECK-NEXT: %"op16562(op17720)" = xor i32 -1, %"op17720(op13219, op18080)"
-; CHECK-NEXT: %"op17430(op16562, op18080)" = add i32 %"op16562(op17720)", %"op18080(op12556, op18131)"
-; CHECK-NEXT: %"op10412(op17430)" = add i32 %"op17430(op16562, op18080)", undef
-; CHECK-NEXT: %"op17720(op10412, op17720)" = mul i32 %"op10412(op17430)", %"op17720(op13219, op18080)"
-; CHECK-NEXT: %"op16562(op17720)1" = xor i32 -1, %"op17720(op10412, op17720)"
-; CHECK-NEXT: %"op17430(op10412, op16562)" = add i32 %"op10412(op17430)", %"op16562(op17720)1"
-; CHECK-NEXT: %"op10412(op17430)2" = add i32 %"op17430(op10412, op16562)", undef
-; CHECK-NEXT: %"op10412(op10412)" = add i32 %"op10412(op17430)2", undef
-; CHECK-NEXT: %"op10412(op10412)3" = add i32 %"op10412(op10412)", undef
-; CHECK-NEXT: %"op17720(op10412, op17720)4" = mul i32 %"op10412(op17430)2", %"op17720(op10412, op17720)"
-; CHECK-NEXT: %"op17720(op10412, op17720)5" = mul i32 %"op10412(op10412)3", %"op17720(op10412, op17720)4"
-; CHECK-NEXT: %"op16562(op17720)6" = xor i32 -1, %"op17720(op10412, op17720)5"
-; CHECK-NEXT: %"op17430(op10412, op16562)7" = add i32 %"op10412(op10412)3", %"op16562(op17720)6"
-; CHECK-NEXT: %"op10412(op17430)8" = add i32 %"op17430(op10412, op16562)7", undef
-; CHECK-NEXT: %"op17720(op10412, op17720)9" = mul i32 %"op10412(op17430)8", %"op17720(op10412, op17720)5"
-; CHECK-NEXT: %"op16562(op17720)10" = xor i32 -1, %"op17720(op10412, op17720)9"
-; CHECK-NEXT: %"op17430(op10412, op16562)11" = add i32 %"op10412(op17430)8", %"op16562(op17720)10"
-; CHECK-NEXT: %"op10412(op17430)12" = add i32 %"op17430(op10412, op16562)11", undef
-; CHECK-NEXT: %"op17720(op10412, op17720)13" = mul i32 %"op10412(op17430)12", %"op17720(op10412, op17720)9"
-; CHECK-NEXT: %"op16562(op17720)14" = xor i32 -1, %"op17720(op10412, op17720)13"
-; CHECK-NEXT: %"op17430(op10412, op16562)15" = add i32 %"op10412(op17430)12", %"op16562(op17720)14"
-; CHECK-NEXT: %"op10412(op17430)16" = add i32 %"op17430(op10412, op16562)15", undef
-; CHECK-NEXT: %"op17720(op10412, op17720)17" = mul i32 %"op10412(op17430)16", %"op17720(op10412, op17720)13"
-; CHECK-NEXT: %"op16562(op17720)18" = xor i32 -1, %"op17720(op10412, op17720)17"
-; CHECK-NEXT: %"op17430(op10412, op16562)19" = add i32 %"op10412(op17430)16", %"op16562(op17720)18"
-; CHECK-NEXT: %"op10412(op17430)20" = add i32 %"op17430(op10412, op16562)19", undef
-; CHECK-NEXT: %"op17720(op10412, op17720)21" = mul i32 %"op10412(op17430)20", %"op17720(op10412, op17720)17"
-; CHECK-NEXT: %"op16562(op17720)22" = xor i32 -1, %"op17720(op10412, op17720)21"
-; CHECK-NEXT: %"op17430(op10412, op16562)23" = add i32 %"op10412(op17430)20", %"op16562(op17720)22"
-; CHECK-NEXT: %"op18131(op81283)24" = add i32 -9, %"op81283(op18131, vl72693)"
-; CHECK-NEXT: %"op18080(op17430, op18131)" = add i32 %"op17430(op10412, op16562)23", %"op18131(op81283)24"
-; CHECK-NEXT: %"op17720(op17720, op18080)" = mul i32 %"op17720(op10412, op17720)21", %"op18080(op17430, op18131)"
-; CHECK-NEXT: %"op16562(op17720)25" = xor i32 -1, %"op17720(op17720, op18080)"
-; CHECK-NEXT: %"op17430(op16562, op18080)26" = add i32 %"op16562(op17720)25", %"op18080(op17430, op18131)"
-; CHECK-NEXT: %"op10412(op17430)27" = add i32 %"op17430(op16562, op18080)26", undef
-; CHECK-NEXT: %"op17720(op10412, op17720)28" = mul i32 %"op10412(op17430)27", %"op17720(op17720, op18080)"
-; CHECK-NEXT: %"op16562(op17720)29" = xor i32 -1, %"op17720(op10412, op17720)28"
-; CHECK-NEXT: %"op17430(op10412, op16562)30" = add i32 %"op10412(op17430)27", %"op16562(op17720)29"
-; CHECK-NEXT: %"op10412(op17430)31" = add i32 %"op17430(op10412, op16562)30", undef
-; CHECK-NEXT: %"op17720(op10412, op17720)32" = mul i32 %"op10412(op17430)31", %"op17720(op10412, op17720)28"
-; CHECK-NEXT: %"op16562(op17720)33" = xor i32 -1, %"op17720(op10412, op17720)32"
-; CHECK-NEXT: %"op17430(op10412, op16562)34" = add i32 %"op10412(op17430)31", %"op16562(op17720)33"
-; CHECK-NEXT: %"op10412(op17430)35" = add i32 %"op17430(op10412, op16562)34", undef
-; CHECK-NEXT: %"op17720(op10412, op17720)36" = mul i32 %"op10412(op17430)35", %"op17720(op10412, op17720)32"
-; CHECK-NEXT: %"op16562(op17720)37" = xor i32 -1, %"op17720(op10412, op17720)36"
-; CHECK-NEXT: %"op17430(op10412, op16562)38" = add i32 %"op10412(op17430)35", %"op16562(op17720)37"
-; CHECK-NEXT: %"op10412(op17430)39" = add i32 %"op17430(op10412, op16562)38", undef
-; CHECK-NEXT: %"op17720(op10412, op17720)40" = mul i32 %"op10412(op17430)39", %"op17720(op10412, op17720)36"
-; CHECK-NEXT: %"op16562(op17720)41" = xor i32 -1, %"op17720(op10412, op17720)40"
-; CHECK-NEXT: %"op17430(op10412, op16562)42" = add i32 %"op10412(op17430)39", %"op16562(op17720)41"
-; CHECK-NEXT: %"op18131(op81283)43" = add i32 -14, %"op81283(op18131, vl72693)"
-; CHECK-NEXT: %"op18080(op17430, op18131)44" = add i32 %"op17430(op10412, op16562)42", %"op18131(op81283)43"
-; CHECK-NEXT: %"op17720(op17720, op18080)45" = mul i32 %"op17720(op10412, op17720)40", %"op18080(op17430, op18131)44"
-; CHECK-NEXT: %"op16562(op17720)46" = xor i32 -1, %"op17720(op17720, op18080)45"
-; CHECK-NEXT: %"op17430(op16562, op18080)47" = add i32 %"op16562(op17720)46", %"op18080(op17430, op18131)44"
-; CHECK-NEXT: %"op10412(op17430)48" = add i32 %"op17430(op16562, op18080)47", undef
-; CHECK-NEXT: %"op17720(op10412, op17720)49" = mul i32 %"op10412(op17430)48", %"op17720(op17720, op18080)45"
-; CHECK-NEXT: %"op16562(op17720)50" = xor i32 -1, %"op17720(op10412, op17720)49"
-; CHECK-NEXT: %"op17430(op10412, op16562)51" = add i32 %"op10412(op17430)48", %"op16562(op17720)50"
-; CHECK-NEXT: %"op10412(op17430)52" = add i32 %"op17430(op10412, op16562)51", undef
-; CHECK-NEXT: %"op17720(op10412, op17720)53" = mul i32 %"op10412(op17430)52", %"op17720(op10412, op17720)49"
-; CHECK-NEXT: %"op16562(op17720)54" = xor i32 -1, %"op17720(op10412, op17720)53"
-; CHECK-NEXT: %"op17430(op10412, op16562)55" = add i32 %"op10412(op17430)52", %"op16562(op17720)54"
-; CHECK-NEXT: %"op10412(op17430)56" = add i32 %"op17430(op10412, op16562)55", undef
-; CHECK-NEXT: %"op17720(op10412, op17720)57" = mul i32 %"op10412(op17430)56", %"op17720(op10412, op17720)53"
-; CHECK-NEXT: %"op16562(op17720)58" = xor i32 -1, %"op17720(op10412, op17720)57"
-; CHECK-NEXT: %"op17430(op10412, op16562)59" = add i32 %"op10412(op17430)56", %"op16562(op17720)58"
-; CHECK-NEXT: %"op10412(op17430)60" = add i32 %"op17430(op10412, op16562)59", undef
-; CHECK-NEXT: %"op17720(op10412, op17720)61" = mul i32 %"op10412(op17430)60", %"op17720(op10412, op17720)57"
-; CHECK-NEXT: %"op16562(op17720)62" = xor i32 -1, %"op17720(op10412, op17720)61"
-; CHECK-NEXT: %"op17430(op10412, op16562)63" = add i32 %"op10412(op17430)60", %"op16562(op17720)62"
-; CHECK-NEXT: %"op10412(op17430)64" = add i32 %"op17430(op10412, op16562)63", undef
-; CHECK-NEXT: %"op17720(op10412, op17720)65" = mul i32 %"op10412(op17430)64", %"op17720(op10412, op17720)61"
-; CHECK-NEXT: %"op16562(op17720)66" = xor i32 -1, %"op17720(op10412, op17720)65"
-; CHECK-NEXT: %"op17430(op10412, op16562)67" = add i32 %"op10412(op17430)64", %"op16562(op17720)66"
-; CHECK-NEXT: %"op10412(op17430)68" = add i32 %"op17430(op10412, op16562)67", undef
-; CHECK-NEXT: %"op10412(op10412)69" = add i32 %"op10412(op17430)68", undef
-; CHECK-NEXT: %"op18131(op81283)70" = add i32 -21, %"op81283(op18131, vl72693)"
-; CHECK-NEXT: %"op18080(op10412, op18131)" = add i32 %"op10412(op10412)69", %"op18131(op81283)70"
-; CHECK-NEXT: store i32 %"op18080(op10412, op18131)", ptr [[A0]], align 4
+; CHECK-NEXT: %"op17327(op85825, vl74787)" = phi i32 [ %"op85825(op11283, op78175)", %[[BB16110]] ], [ %"vl74787([[A1]], 1)", %[[BB76951]] ]
+; CHECK-NEXT: %"op17327(op78175, vl74787)" = phi i32 [ %"op78175(op17327)70", %[[BB16110]] ], [ %"vl74787([[A1]], 1)", %[[BB76951]] ]
+; CHECK-NEXT: %"op97159(op17327)" = mul i32 %"op17327(op85825, vl74787)", undef
+; CHECK-NEXT: %"op26718(op97159)" = xor i32 -1, %"op97159(op17327)"
+; CHECK-NEXT: %"op96390(op17327, op26718)" = add i32 %"op17327(op85825, vl74787)", %"op26718(op97159)"
+; CHECK-NEXT: %"op78175(op17327)" = add i32 -1, %"op17327(op78175, vl74787)"
+; CHECK-NEXT: %"op85825(op78175, op96390)" = add i32 %"op78175(op17327)", %"op96390(op17327, op26718)"
+; CHECK-NEXT: %"op11951(op85825, op97159)" = mul i32 %"op85825(op78175, op96390)", %"op97159(op17327)"
+; CHECK-NEXT: %"op26718(op11951)" = xor i32 -1, %"op11951(op85825, op97159)"
+; CHECK-NEXT: %"op14739(op26718, op85825)" = add i32 %"op26718(op11951)", %"op85825(op78175, op96390)"
+; CHECK-NEXT: %"op11283(op14739)" = add i32 %"op14739(op26718, op85825)", undef
+; CHECK-NEXT: %"op11951(op11283, op11951)" = mul i32 %"op11283(op14739)", %"op11951(op85825, op97159)"
+; CHECK-NEXT: %"op26718(op11951)1" = xor i32 -1, %"op11951(op11283, op11951)"
+; CHECK-NEXT: %"op14739(op11283, op26718)" = add i32 %"op11283(op14739)", %"op26718(op11951)1"
+; CHECK-NEXT: %"op11283(op14739)2" = add i32 %"op14739(op11283, op26718)", undef
+; CHECK-NEXT: %"op11283(op11283)" = add i32 %"op11283(op14739)2", undef
+; CHECK-NEXT: %"op11283(op11283)3" = add i32 %"op11283(op11283)", undef
+; CHECK-NEXT: %"op11951(op11283, op11951)4" = mul i32 %"op11283(op14739)2", %"op11951(op11283, op11951)"
+; CHECK-NEXT: %"op11951(op11283, op11951)5" = mul i32 %"op11283(op11283)3", %"op11951(op11283, op11951)4"
+; CHECK-NEXT: %"op26718(op11951)6" = xor i32 -1, %"op11951(op11283, op11951)5"
+; CHECK-NEXT: %"op14739(op11283, op26718)7" = add i32 %"op11283(op11283)3", %"op26718(op11951)6"
+; CHECK-NEXT: %"op11283(op14739)8" = add i32 %"op14739(op11283, op26718)7", undef
+; CHECK-NEXT: %"op11951(op11283, op11951)9" = mul i32 %"op11283(op14739)8", %"op11951(op11283, op11951)5"
+; CHECK-NEXT: %"op26718(op11951)10" = xor i32 -1, %"op11951(op11283, op11951)9"
+; CHECK-NEXT: %"op14739(op11283, op26718)11" = add i32 %"op11283(op14739)8", %"op26718(op11951)10"
+; CHECK-NEXT: %"op11283(op14739)12" = add i32 %"op14739(op11283, op26718)11", undef
+; CHECK-NEXT: %"op11951(op11283, op11951)13" = mul i32 %"op11283(op14739)12", %"op11951(op11283, op11951)9"
+; CHECK-NEXT: %"op26718(op11951)14" = xor i32 -1, %"op11951(op11283, op11951)13"
+; CHECK-NEXT: %"op14739(op11283, op26718)15" = add i32 %"op11283(op14739)12", %"op26718(op11951)14"
+; CHECK-NEXT: %"op11283(op14739)16" = add i32 %"op14739(op11283, op26718)15", undef
+; CHECK-NEXT: %"op11951(op11283, op11951)17" = mul i32 %"op11283(op14739)16", %"op11951(op11283, op11951)13"
+; CHECK-NEXT: %"op26718(op11951)18" = xor i32 -1, %"op11951(op11283, op11951)17"
+; CHECK-NEXT: %"op14739(op11283, op26718)19" = add i32 %"op11283(op14739)16", %"op26718(op11951)18"
+; CHECK-NEXT: %"op11283(op14739)20" = add i32 %"op14739(op11283, op26718)19", undef
+; CHECK-NEXT: %"op11951(op11283, op11951)21" = mul i32 %"op11283(op14739)20", %"op11951(op11283, op11951)17"
+; CHECK-NEXT: %"op26718(op11951)22" = xor i32 -1, %"op11951(op11283, op11951)21"
+; CHECK-NEXT: %"op14739(op11283, op26718)23" = add i32 %"op11283(op14739)20", %"op26718(op11951)22"
+; CHECK-NEXT: %"op78175(op17327)24" = add i32 -9, %"op17327(op78175, vl74787)"
+; CHECK-NEXT: %"op85825(op14739, op78175)" = add i32 %"op14739(op11283, op26718)23", %"op78175(op17327)24"
+; CHECK-NEXT: %"op11951(op11951, op85825)" = mul i32 %"op11951(op11283, op11951)21", %"op85825(op14739, op78175)"
+; CHECK-NEXT: %"op26718(op11951)25" = xor i32 -1, %"op11951(op11951, op85825)"
+; CHECK-NEXT: %"op14739(op26718, op85825)26" = add i32 %"op26718(op11951)25", %"op85825(op14739, op78175)"
+; CHECK-NEXT: %"op11283(op14739)27" = add i32 %"op14739(op26718, op85825)26", undef
+; CHECK-NEXT: %"op11951(op11283, op11951)28" = mul i32 %"op11283(op14739)27", %"op11951(op11951, op85825)"
+; CHECK-NEXT: %"op26718(op11951)29" = xor i32 -1, %"op11951(op11283, op11951)28"
+; CHECK-NEXT: %"op14739(op11283, op26718)30" = add i32 %"op11283(op14739)27", %"op26718(op11951)29"
+; CHECK-NEXT: %"op11283(op14739)31" = add i32 %"op14739(op11283, op26718)30", undef
+; CHECK-NEXT: %"op11951(op11283, op11951)32" = mul i32 %"op11283(op14739)31", %"op11951(op11283, op11951)28"
+; CHECK-NEXT: %"op26718(op11951)33" = xor i32 -1, %"op11951(op11283, op11951)32"
+; CHECK-NEXT: %"op14739(op11283, op26718)34" = add i32 %"op11283(op14739)31", %"op26718(op11951)33"
+; CHECK-NEXT: %"op11283(op14739)35" = add i32 %"op14739(op11283, op26718)34", undef
+; CHECK-NEXT: %"op11951(op11283, op11951)36" = mul i32 %"op11283(op14739)35", %"op11951(op11283, op11951)32"
+; CHECK-NEXT: %"op26718(op11951)37" = xor i32 -1, %"op11951(op11283, op11951)36"
+; CHECK-NEXT: %"op14739(op11283, op26718)38" = add i32 %"op11283(op14739)35", %"op26718(op11951)37"
+; CHECK-NEXT: %"op11283(op14739)39" = add i32 %"op14739(op11283, op26718)38", undef
+; CHECK-NEXT: %"op11951(op11283, op11951)40" = mul i32 %"op11283(op14739)39", %"op11951(op11283, op11951)36"
+; CHECK-NEXT: %"op26718(op11951)41" = xor i32 -1, %"op11951(op11283, op11951)40"
+; CHECK-NEXT: %"op14739(op11283, op26718)42" = add i32 %"op11283(op14739)39", %"op26718(op11951)41"
+; CHECK-NEXT: %"op78175(op17327)43" = add i32 -14, %"op17327(op78175, vl74787)"
+; CHECK-NEXT: %"op85825(op14739, op78175)44" = add i32 %"op14739(op11283, op26718)42", %"op78175(op17327)43"
+; CHECK-NEXT: %"op11951(op11951, op85825)45" = mul i32 %"op11951(op11283, op11951)40", %"op85825(op14739, op78175)44"
+; CHECK-NEXT: %"op26718(op11951)46" = xor i32 -1, %"op11951(op11951, op85825)45"
+; CHECK-NEXT: %"op14739(op26718, op85825)47" = add i32 %"op26718(op11951)46", %"op85825(op14739, op78175)44"
+; CHECK-NEXT: %"op11283(op14739)48" = add i32 %"op14739(op26718, op85825)47", undef
+; CHECK-NEXT: %"op11951(op11283, op11951)49" = mul i32 %"op11283(op14739)48", %"op11951(op11951, op85825)45"
+; CHECK-NEXT: %"op26718(op11951)50" = xor i32 -1, %"op11951(op11283, op11951)49"
+; CHECK-NEXT: %"op14739(op11283, op26718)51" = add i32 %"op11283(op14739)48", %"op26718(op11951)50"
+; CHECK-NEXT: %"op11283(op14739)52" = add i32 %"op14739(op11283, op26718)51", undef
+; CHECK-NEXT: %"op11951(op11283, op11951)53" = mul i32 %"op11283(op14739)52", %"op11951(op11283, op11951)49"
+; CHECK-NEXT: %"op26718(op11951)54" = xor i32 -1, %"op11951(op11283, op11951)53"
+; CHECK-NEXT: %"op14739(op11283, op26718)55" = add i32 %"op11283(op14739)52", %"op26718(op11951)54"
+; CHECK-NEXT: %"op11283(op14739)56" = add i32 %"op14739(op11283, op26718)55", undef
+; CHECK-NEXT: %"op11951(op11283, op11951)57" = mul i32 %"op11283(op14739)56", %"op11951(op11283, op11951)53"
+; CHECK-NEXT: %"op26718(op11951)58" = xor i32 -1, %"op11951(op11283, op11951)57"
+; CHECK-NEXT: %"op14739(op11283, op26718)59" = add i32 %"op11283(op14739)56", %"op26718(op11951)58"
+; CHECK-NEXT: %"op11283(op14739)60" = add i32 %"op14739(op11283, op26718)59", undef
+; CHECK-NEXT: %"op11951(op11283, op11951)61" = mul i32 %"op11283(op14739)60", %"op11951(op11283, op11951)57"
+; CHECK-NEXT: %"op26718(op11951)62" = xor i32 -1, %"op11951(op11283, op11951)61"
+; CHECK-NEXT: %"op14739(op11283, op26718)63" = add i32 %"op11283(op14739)60", %"op26718(op11951)62"
+; CHECK-NEXT: %"op11283(op14739)64" = add i32 %"op14739(op11283, op26718)63", undef
+; CHECK-NEXT: %"op11951(op11283, op11951)65" = mul i32 %"op11283(op14739)64", %"op11951(op11283, op11951)61"
+; CHECK-NEXT: %"op26718(op11951)66" = xor i32 -1, %"op11951(op11283, op11951)65"
+; CHECK-NEXT: %"op14739(op11283, op26718)67" = add i32 %"op11283(op14739)64", %"op26718(op11951)66"
+; CHECK-NEXT: %"op11283(op14739)68" = add i32 %"op14739(op11283, op26718)67", undef
+; CHECK-NEXT: %"op11283(op11283)69" = add i32 %"op11283(op14739)68", undef
+; CHECK-NEXT: %"op78175(op17327)70" = add i32 -21, %"op17327(op78175, vl74787)"
+; CHECK-NEXT: %"op85825(op11283, op78175)" = add i32 %"op11283(op11283)69", %"op78175(op17327)70"
+; CHECK-NEXT: store i32 %"op85825(op11283, op78175)", ptr [[A0]], align 4
; CHECK-NEXT: br label %[[BB16110]]
;
bb:
diff --git a/llvm/test/Transforms/IRNormalizer/reordering-basic.ll b/llvm/test/Transforms/IRNormalizer/reordering-basic.ll
index 06e67e0feb7e4..f6d9527ed671f 100644
--- a/llvm/test/Transforms/IRNormalizer/reordering-basic.ll
+++ b/llvm/test/Transforms/IRNormalizer/reordering-basic.ll
@@ -5,11 +5,11 @@ define double @foo(double %a0, double %a1) {
; CHECK-LABEL: define double @foo(
; CHECK-SAME: double [[A0:%.*]], double [[A1:%.*]]) {
; CHECK-NEXT: [[BB17254:.*:]]
-; CHECK-NEXT: %"vl93562([[A0]], 2.000000e+00)" = fmul double [[A0]], 2.000000e+00
-; CHECK-NEXT: %"op95858(vl93562)" = fmul double 6.000000e+00, %"vl93562([[A0]], 2.000000e+00)"
+; CHECK-NEXT: %"vl16288([[A0]], 2.000000e+00)" = fmul double [[A0]], 2.000000e+00
+; CHECK-NEXT: %"op44980(vl16288)" = fmul double 6.000000e+00, %"vl16288([[A0]], 2.000000e+00)"
; CHECK-NEXT: [[A:%.*]] = fmul double [[A0]], [[A1]]
; CHECK-NEXT: [[C:%.*]] = fmul double 6.000000e+00, [[A]]
-; CHECK-NEXT: ret double %"op95858(vl93562)"
+; CHECK-NEXT: ret double %"op44980(vl16288)"
;
entry:
%a = fmul double %a0, %a1
@@ -30,14 +30,14 @@ define double @baz(double %x) {
; CHECK-NEXT: [[IFCOND:%.*]] = fcmp one double [[A0]], 0.000000e+00
; CHECK-NEXT: br i1 [[IFCOND]], label %[[BB47054:.*]], label %[[BB470541:.*]]
; CHECK: [[BB47054]]:
-; CHECK-NEXT: %"vl16994bir()" = call double @bir()
+; CHECK-NEXT: %"vl12417bir()" = call double @bir()
; CHECK-NEXT: br label %[[BB17254:.*]]
; CHECK: [[BB470541]]:
-; CHECK-NEXT: %"vl88592bar()" = call double @bar()
+; CHECK-NEXT: %"vl26594bar()" = call double @bar()
; CHECK-NEXT: br label %[[BB17254]]
; CHECK: [[BB17254]]:
-; CHECK-NEXT: %"op16411(vl16994, vl88592)" = phi double [ %"vl16994bir()", %[[BB47054]] ], [ %"vl88592bar()", %[[BB470541]] ]
-; CHECK-NEXT: ret double %"op16411(vl16994, vl88592)"
+; CHECK-NEXT: %"op24395(vl12417, vl26594)" = phi double [ %"vl12417bir()", %[[BB47054]] ], [ %"vl26594bar()", %[[BB470541]] ]
+; CHECK-NEXT: ret double %"op24395(vl12417, vl26594)"
;
entry:
%ifcond = fcmp one double %x, 0.000000e+00
diff --git a/llvm/test/Transforms/IRNormalizer/reordering.ll b/llvm/test/Transforms/IRNormalizer/reordering.ll
index a3dbcb5494875..f019b6acf5f63 100644
--- a/llvm/test/Transforms/IRNormalizer/reordering.ll
+++ b/llvm/test/Transforms/IRNormalizer/reordering.ll
@@ -23,7 +23,7 @@ declare void @effecting()
; Place dead instruction(s) before the terminator
define void @call_effecting() {
; CHECK-LABEL: define void @call_effecting() {
-; CHECK-NEXT: bb14885:
+; CHECK-NEXT: bb72598:
; CHECK-NEXT: call void @effecting()
; CHECK-NEXT: [[TMP0:%.*]] = add i32 0, 1
; CHECK-NEXT: ret void
@@ -51,7 +51,7 @@ exit:
define void @dont_move_above_alloca() {
; CHECK-LABEL: define void @dont_move_above_alloca() {
-; CHECK-NEXT: bb14885:
+; CHECK-NEXT: bb72598:
; CHECK-NEXT: [[TMP0:%.*]] = alloca i32, align 4
; CHECK-NEXT: call void @effecting()
; CHECK-NEXT: ret void
@@ -65,7 +65,7 @@ declare void @effecting1()
define void @dont_reorder_effecting() {
; CHECK-LABEL: define void @dont_reorder_effecting() {
-; CHECK-NEXT: bb45003:
+; CHECK-NEXT: bb86996:
; CHECK-NEXT: call void @effecting()
; CHECK-NEXT: call void @effecting1()
; CHECK-NEXT: ret void
@@ -79,7 +79,7 @@ declare void @effecting2(i32)
define void @dont_reorder_effecting1() {
; CHECK-LABEL: define void @dont_reorder_effecting1() {
-; CHECK-NEXT: bb45003:
+; CHECK-NEXT: bb86996:
; CHECK-NEXT: [[ONE:%.*]] = add i32 1, 1
; CHECK-NEXT: call void @effecting2(i32 [[ONE]])
; CHECK-NEXT: [[TWO:%.*]] = add i32 2, 2
@@ -112,11 +112,11 @@ exit:
define void @independentldst(ptr %a, ptr %b) {
; CHECK-LABEL: define void @independentldst(
; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) {
-; CHECK-NEXT: bb10495:
-; CHECK-NEXT: %"vl12961([[B]])" = load i32, ptr [[B]], align 4
-; CHECK-NEXT: store i32 %"vl12961([[B]])", ptr [[A]], align 4
-; CHECK-NEXT: %"vl89528([[A]])" = load i32, ptr [[A]], align 4
-; CHECK-NEXT: store i32 %"vl89528([[A]])", ptr [[B]], align 4
+; CHECK-NEXT: bb76827:
+; CHECK-NEXT: %"vl98792([[B]])" = load i32, ptr [[B]], align 4
+; CHECK-NEXT: store i32 %"vl98792([[B]])", ptr [[A]], align 4
+; CHECK-NEXT: %"vl13896([[A]])" = load i32, ptr [[A]], align 4
+; CHECK-NEXT: store i32 %"vl13896([[A]])", ptr [[B]], align 4
; CHECK-NEXT: ret void
;
%2 = load i32, ptr %a
@@ -129,12 +129,12 @@ define void @independentldst(ptr %a, ptr %b) {
define void @multiple_use_ld(ptr %a, ptr %b) {
; CHECK-LABEL: define void @multiple_use_ld(
; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) {
-; CHECK-NEXT: bb14927:
-; CHECK-NEXT: %"vl16793([[A]])" = load i32, ptr [[A]], align 4
-; CHECK-NEXT: store i32 %"vl16793([[A]])", ptr [[A]], align 4
-; CHECK-NEXT: %"vl89528([[B]])" = load i32, ptr [[B]], align 4
-; CHECK-NEXT: store i32 %"vl89528([[B]])", ptr [[B]], align 4
-; CHECK-NEXT: store i32 %"vl16793([[A]])", ptr [[A]], align 4
+; CHECK-NEXT: bb96924:
+; CHECK-NEXT: %"vl10390([[A]])" = load i32, ptr [[A]], align 4
+; CHECK-NEXT: store i32 %"vl10390([[A]])", ptr [[A]], align 4
+; CHECK-NEXT: %"vl13896([[B]])" = load i32, ptr [[B]], align 4
+; CHECK-NEXT: store i32 %"vl13896([[B]])", ptr [[B]], align 4
+; CHECK-NEXT: store i32 %"vl10390([[A]])", ptr [[A]], align 4
; CHECK-NEXT: ret void
;
%2 = load i32, ptr %a
@@ -150,10 +150,10 @@ define void @multiple_use_ld(ptr %a, ptr %b) {
define void @undef_st(ptr %a, ptr %b) {
; CHECK-LABEL: define void @undef_st(
; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) {
-; CHECK-NEXT: bb10495:
+; CHECK-NEXT: bb76827:
; CHECK-NEXT: store i32 undef, ptr [[B]], align 4
-; CHECK-NEXT: %"vl16028([[A]])" = load i32, ptr [[A]], align 4
-; CHECK-NEXT: store i32 %"vl16028([[A]])", ptr [[A]], align 4
+; CHECK-NEXT: %"vl98662([[A]])" = load i32, ptr [[A]], align 4
+; CHECK-NEXT: store i32 %"vl98662([[A]])", ptr [[A]], align 4
; CHECK-NEXT: ret void
;
%2 = load i32, ptr %a
diff --git a/llvm/test/tools/llvm-ir2vec/entities.ll b/llvm/test/tools/llvm-ir2vec/entities.ll
index 8dbce57302f6f..6b2e2e4db2ff6 100644
--- a/llvm/test/tools/llvm-ir2vec/entities.ll
+++ b/llvm/test/tools/llvm-ir2vec/entities.ll
@@ -1,113 +1,114 @@
; RUN: llvm-ir2vec entities | FileCheck %s
-CHECK: 110
-CHECK-NEXT: Ret 0
-CHECK-NEXT: Br 1
-CHECK-NEXT: Switch 2
-CHECK-NEXT: IndirectBr 3
-CHECK-NEXT: Invoke 4
-CHECK-NEXT: Resume 5
-CHECK-NEXT: Unreachable 6
-CHECK-NEXT: CleanupRet 7
-CHECK-NEXT: CatchRet 8
-CHECK-NEXT: CatchSwitch 9
-CHECK-NEXT: CallBr 10
-CHECK-NEXT: FNeg 11
-CHECK-NEXT: Add 12
-CHECK-NEXT: FAdd 13
-CHECK-NEXT: Sub 14
-CHECK-NEXT: FSub 15
-CHECK-NEXT: Mul 16
-CHECK-NEXT: FMul 17
-CHECK-NEXT: UDiv 18
-CHECK-NEXT: SDiv 19
-CHECK-NEXT: FDiv 20
-CHECK-NEXT: URem 21
-CHECK-NEXT: SRem 22
-CHECK-NEXT: FRem 23
-CHECK-NEXT: Shl 24
-CHECK-NEXT: LShr 25
-CHECK-NEXT: AShr 26
-CHECK-NEXT: And 27
-CHECK-NEXT: Or 28
-CHECK-NEXT: Xor 29
-CHECK-NEXT: Alloca 30
-CHECK-NEXT: Load 31
-CHECK-NEXT: Store 32
-CHECK-NEXT: GetElementPtr 33
-CHECK-NEXT: Fence 34
-CHECK-NEXT: AtomicCmpXchg 35
-CHECK-NEXT: AtomicRMW 36
-CHECK-NEXT: Trunc 37
-CHECK-NEXT: ZExt 38
-CHECK-NEXT: SExt 39
-CHECK-NEXT: FPToUI 40
-CHECK-NEXT: FPToSI 41
-CHECK-NEXT: UIToFP 42
-CHECK-NEXT: SIToFP 43
-CHECK-NEXT: FPTrunc 44
-CHECK-NEXT: FPExt 45
-CHECK-NEXT: PtrToInt 46
-CHECK-NEXT: PtrToAddr 47
-CHECK-NEXT: IntToPtr 48
-CHECK-NEXT: BitCast 49
-CHECK-NEXT: AddrSpaceCast 50
-CHECK-NEXT: CleanupPad 51
-CHECK-NEXT: CatchPad 52
-CHECK-NEXT: ICmp 53
-CHECK-NEXT: FCmp 54
-CHECK-NEXT: PHI 55
-CHECK-NEXT: Call 56
-CHECK-NEXT: Select 57
-CHECK-NEXT: UserOp1 58
-CHECK-NEXT: UserOp2 59
-CHECK-NEXT: VAArg 60
-CHECK-NEXT: ExtractElement 61
-CHECK-NEXT: InsertElement 62
-CHECK-NEXT: ShuffleVector 63
-CHECK-NEXT: ExtractValue 64
-CHECK-NEXT: InsertValue 65
-CHECK-NEXT: LandingPad 66
-CHECK-NEXT: Freeze 67
-CHECK-NEXT: FloatTy 68
-CHECK-NEXT: VoidTy 69
-CHECK-NEXT: LabelTy 70
-CHECK-NEXT: MetadataTy 71
-CHECK-NEXT: VectorTy 72
-CHECK-NEXT: TokenTy 73
-CHECK-NEXT: IntegerTy 74
-CHECK-NEXT: FunctionTy 75
-CHECK-NEXT: PointerTy 76
-CHECK-NEXT: StructTy 77
-CHECK-NEXT: ArrayTy 78
-CHECK-NEXT: UnknownTy 79
-CHECK-NEXT: Function 80
-CHECK-NEXT: Pointer 81
-CHECK-NEXT: Constant 82
-CHECK-NEXT: Variable 83
-CHECK-NEXT: FCMP_false 84
-CHECK-NEXT: FCMP_oeq 85
-CHECK-NEXT: FCMP_ogt 86
-CHECK-NEXT: FCMP_oge 87
-CHECK-NEXT: FCMP_olt 88
-CHECK-NEXT: FCMP_ole 89
-CHECK-NEXT: FCMP_one 90
-CHECK-NEXT: FCMP_ord 91
-CHECK-NEXT: FCMP_uno 92
-CHECK-NEXT: FCMP_ueq 93
-CHECK-NEXT: FCMP_ugt 94
-CHECK-NEXT: FCMP_uge 95
-CHECK-NEXT: FCMP_ult 96
-CHECK-NEXT: FCMP_ule 97
-CHECK-NEXT: FCMP_une 98
-CHECK-NEXT: FCMP_true 99
-CHECK-NEXT: ICMP_eq 100
-CHECK-NEXT: ICMP_ne 101
-CHECK-NEXT: ICMP_ugt 102
-CHECK-NEXT: ICMP_uge 103
-CHECK-NEXT: ICMP_ult 104
-CHECK-NEXT: ICMP_ule 105
-CHECK-NEXT: ICMP_sgt 106
-CHECK-NEXT: ICMP_sge 107
-CHECK-NEXT: ICMP_slt 108
-CHECK-NEXT: ICMP_sle 109
+CHECK: 111
+CHECK-NEXT: Ret 0
+CHECK-NEXT: UncondBr 1
+CHECK-NEXT: CondBr 2
+CHECK-NEXT: Switch 3
+CHECK-NEXT: IndirectBr 4
+CHECK-NEXT: Invoke 5
+CHECK-NEXT: Resume 6
+CHECK-NEXT: Unreachable 7
+CHECK-NEXT: CleanupRet 8
+CHECK-NEXT: CatchRet 9
+CHECK-NEXT: CatchSwitch 10
+CHECK-NEXT: CallBr 11
+CHECK-NEXT: FNeg 12
+CHECK-NEXT: Add 13
+CHECK-NEXT: FAdd 14
+CHECK-NEXT: Sub 15
+CHECK-NEXT: FSub 16
+CHECK-NEXT: Mul 17
+CHECK-NEXT: FMul 18
+CHECK-NEXT: UDiv 19
+CHECK-NEXT: SDiv 20
+CHECK-NEXT: FDiv 21
+CHECK-NEXT: URem 22
+CHECK-NEXT: SRem 23
+CHECK-NEXT: FRem 24
+CHECK-NEXT: Shl 25
+CHECK-NEXT: LShr 26
+CHECK-NEXT: AShr 27
+CHECK-NEXT: And 28
+CHECK-NEXT: Or 29
+CHECK-NEXT: Xor 30
+CHECK-NEXT: Alloca 31
+CHECK-NEXT: Load 32
+CHECK-NEXT: Store 33
+CHECK-NEXT: GetElementPtr 34
+CHECK-NEXT: Fence 35
+CHECK-NEXT: AtomicCmpXchg 36
+CHECK-NEXT: AtomicRMW 37
+CHECK-NEXT: Trunc 38
+CHECK-NEXT: ZExt 39
+CHECK-NEXT: SExt 40
+CHECK-NEXT: FPToUI 41
+CHECK-NEXT: FPToSI 42
+CHECK-NEXT: UIToFP 43
+CHECK-NEXT: SIToFP 44
+CHECK-NEXT: FPTrunc 45
+CHECK-NEXT: FPExt 46
+CHECK-NEXT: PtrToInt 47
+CHECK-NEXT: PtrToAddr 48
+CHECK-NEXT: IntToPtr 49
+CHECK-NEXT: BitCast 50
+CHECK-NEXT: AddrSpaceCast 51
+CHECK-NEXT: CleanupPad 52
+CHECK-NEXT: CatchPad 53
+CHECK-NEXT: ICmp 54
+CHECK-NEXT: FCmp 55
+CHECK-NEXT: PHI 56
+CHECK-NEXT: Call 57
+CHECK-NEXT: Select 58
+CHECK-NEXT: UserOp1 59
+CHECK-NEXT: UserOp2 60
+CHECK-NEXT: VAArg 61
+CHECK-NEXT: ExtractElement 62
+CHECK-NEXT: InsertElement 63
+CHECK-NEXT: ShuffleVector 64
+CHECK-NEXT: ExtractValue 65
+CHECK-NEXT: InsertValue 66
+CHECK-NEXT: LandingPad 67
+CHECK-NEXT: Freeze 68
+CHECK-NEXT: FloatTy 69
+CHECK-NEXT: VoidTy 70
+CHECK-NEXT: LabelTy 71
+CHECK-NEXT: MetadataTy 72
+CHECK-NEXT: VectorTy 73
+CHECK-NEXT: TokenTy 74
+CHECK-NEXT: IntegerTy 75
+CHECK-NEXT: FunctionTy 76
+CHECK-NEXT: PointerTy 77
+CHECK-NEXT: StructTy 78
+CHECK-NEXT: ArrayTy 79
+CHECK-NEXT: UnknownTy 80
+CHECK-NEXT: Function 81
+CHECK-NEXT: Pointer 82
+CHECK-NEXT: Constant 83
+CHECK-NEXT: Variable 84
+CHECK-NEXT: FCMP_false 85
+CHECK-NEXT: FCMP_oeq 86
+CHECK-NEXT: FCMP_ogt 87
+CHECK-NEXT: FCMP_oge 88
+CHECK-NEXT: FCMP_olt 89
+CHECK-NEXT: FCMP_ole 90
+CHECK-NEXT: FCMP_one 91
+CHECK-NEXT: FCMP_ord 92
+CHECK-NEXT: FCMP_uno 93
+CHECK-NEXT: FCMP_ueq 94
+CHECK-NEXT: FCMP_ugt 95
+CHECK-NEXT: FCMP_uge 96
+CHECK-NEXT: FCMP_ult 97
+CHECK-NEXT: FCMP_ule 98
+CHECK-NEXT: FCMP_une 99
+CHECK-NEXT: FCMP_true 100
+CHECK-NEXT: ICMP_eq 101
+CHECK-NEXT: ICMP_ne 102
+CHECK-NEXT: ICMP_ugt 103
+CHECK-NEXT: ICMP_uge 104
+CHECK-NEXT: ICMP_ult 105
+CHECK-NEXT: ICMP_ule 106
+CHECK-NEXT: ICMP_sgt 107
+CHECK-NEXT: ICMP_sge 108
+CHECK-NEXT: ICMP_slt 109
+CHECK-NEXT: ICMP_sle 110
diff --git a/llvm/test/tools/llvm-ir2vec/triplets.ll b/llvm/test/tools/llvm-ir2vec/triplets.ll
index 7b476f60a07b3..7632e236c4107 100644
--- a/llvm/test/tools/llvm-ir2vec/triplets.ll
+++ b/llvm/test/tools/llvm-ir2vec/triplets.ll
@@ -25,41 +25,41 @@ entry:
}
; TRIPLETS: MAX_RELATION=3
-; TRIPLETS-NEXT: 12 74 0
-; TRIPLETS-NEXT: 12 83 2
-; TRIPLETS-NEXT: 12 83 3
-; TRIPLETS-NEXT: 12 0 1
-; TRIPLETS-NEXT: 0 69 0
-; TRIPLETS-NEXT: 0 83 2
-; TRIPLETS-NEXT: 16 74 0
-; TRIPLETS-NEXT: 16 83 2
-; TRIPLETS-NEXT: 16 83 3
-; TRIPLETS-NEXT: 16 0 1
-; TRIPLETS-NEXT: 0 69 0
-; TRIPLETS-NEXT: 0 83 2
-; TRIPLETS-NEXT: 30 76 0
-; TRIPLETS-NEXT: 30 82 2
-; TRIPLETS-NEXT: 30 30 1
-; TRIPLETS-NEXT: 30 76 0
-; TRIPLETS-NEXT: 30 82 2
-; TRIPLETS-NEXT: 30 32 1
-; TRIPLETS-NEXT: 32 69 0
-; TRIPLETS-NEXT: 32 83 2
-; TRIPLETS-NEXT: 32 81 3
-; TRIPLETS-NEXT: 32 32 1
-; TRIPLETS-NEXT: 32 69 0
-; TRIPLETS-NEXT: 32 83 2
-; TRIPLETS-NEXT: 32 81 3
-; TRIPLETS-NEXT: 32 31 1
-; TRIPLETS-NEXT: 31 74 0
-; TRIPLETS-NEXT: 31 81 2
-; TRIPLETS-NEXT: 31 31 1
-; TRIPLETS-NEXT: 31 74 0
-; TRIPLETS-NEXT: 31 81 2
-; TRIPLETS-NEXT: 31 12 1
-; TRIPLETS-NEXT: 12 74 0
-; TRIPLETS-NEXT: 12 83 2
-; TRIPLETS-NEXT: 12 83 3
-; TRIPLETS-NEXT: 12 0 1
-; TRIPLETS-NEXT: 0 69 0
-; TRIPLETS-NEXT: 0 83 2
\ No newline at end of file
+; TRIPLETS-NEXT: 13 75 0
+; TRIPLETS-NEXT: 13 84 2
+; TRIPLETS-NEXT: 13 84 3
+; TRIPLETS-NEXT: 13 0 1
+; TRIPLETS-NEXT: 0 70 0
+; TRIPLETS-NEXT: 0 84 2
+; TRIPLETS-NEXT: 17 75 0
+; TRIPLETS-NEXT: 17 84 2
+; TRIPLETS-NEXT: 17 84 3
+; TRIPLETS-NEXT: 17 0 1
+; TRIPLETS-NEXT: 0 70 0
+; TRIPLETS-NEXT: 0 84 2
+; TRIPLETS-NEXT: 31 77 0
+; TRIPLETS-NEXT: 31 83 2
+; TRIPLETS-NEXT: 31 31 1
+; TRIPLETS-NEXT: 31 77 0
+; TRIPLETS-NEXT: 31 83 2
+; TRIPLETS-NEXT: 31 33 1
+; TRIPLETS-NEXT: 33 70 0
+; TRIPLETS-NEXT: 33 84 2
+; TRIPLETS-NEXT: 33 82 3
+; TRIPLETS-NEXT: 33 33 1
+; TRIPLETS-NEXT: 33 70 0
+; TRIPLETS-NEXT: 33 84 2
+; TRIPLETS-NEXT: 33 82 3
+; TRIPLETS-NEXT: 33 32 1
+; TRIPLETS-NEXT: 32 75 0
+; TRIPLETS-NEXT: 32 82 2
+; TRIPLETS-NEXT: 32 32 1
+; TRIPLETS-NEXT: 32 75 0
+; TRIPLETS-NEXT: 32 82 2
+; TRIPLETS-NEXT: 32 13 1
+; TRIPLETS-NEXT: 13 75 0
+; TRIPLETS-NEXT: 13 84 2
+; TRIPLETS-NEXT: 13 84 3
+; TRIPLETS-NEXT: 13 0 1
+; TRIPLETS-NEXT: 0 70 0
+; TRIPLETS-NEXT: 0 84 2
diff --git a/llvm/tools/llvm-c-test/echo.cpp b/llvm/tools/llvm-c-test/echo.cpp
index bd640cd8d85ec..2f29933c8fe44 100644
--- a/llvm/tools/llvm-c-test/echo.cpp
+++ b/llvm/tools/llvm-c-test/echo.cpp
@@ -560,14 +560,13 @@ struct FunCloner {
Dst = LLVMBuildRet(Builder, CloneValue(LLVMGetOperand(Src, 0)));
break;
}
- case LLVMBr: {
- if (!LLVMIsConditional(Src)) {
- LLVMValueRef SrcOp = LLVMGetOperand(Src, 0);
- LLVMBasicBlockRef SrcBB = LLVMValueAsBasicBlock(SrcOp);
- Dst = LLVMBuildBr(Builder, DeclareBB(SrcBB));
- break;
- }
-
+ case LLVMUncondBr: {
+ LLVMValueRef SrcOp = LLVMGetOperand(Src, 0);
+ LLVMBasicBlockRef SrcBB = LLVMValueAsBasicBlock(SrcOp);
+ Dst = LLVMBuildBr(Builder, DeclareBB(SrcBB));
+ break;
+ }
+ case LLVMCondBr: {
LLVMValueRef Cond = LLVMGetCondition(Src);
LLVMValueRef Else = LLVMGetOperand(Src, 1);
LLVMBasicBlockRef ElseBB = DeclareBB(LLVMValueAsBasicBlock(Else));
diff --git a/llvm/unittests/Analysis/IR2VecTest.cpp b/llvm/unittests/Analysis/IR2VecTest.cpp
index b76da2bc4dd34..694d04b22b720 100644
--- a/llvm/unittests/Analysis/IR2VecTest.cpp
+++ b/llvm/unittests/Analysis/IR2VecTest.cpp
@@ -363,8 +363,8 @@ TEST_F(IR2VecTestFixture, GetInstVec_Symbolic) {
EXPECT_EQ(AddEmb.size(), 2u);
EXPECT_EQ(RetEmb.size(), 2u);
- EXPECT_TRUE(AddEmb.approximatelyEquals(Embedding(2, 25.5)));
- EXPECT_TRUE(RetEmb.approximatelyEquals(Embedding(2, 15.5)));
+ EXPECT_TRUE(AddEmb.approximatelyEquals(Embedding(2, 25.9)));
+ EXPECT_TRUE(RetEmb.approximatelyEquals(Embedding(2, 15.7)));
}
TEST_F(IR2VecTestFixture, GetInstVec_FlowAware) {
@@ -376,8 +376,8 @@ TEST_F(IR2VecTestFixture, GetInstVec_FlowAware) {
EXPECT_EQ(AddEmb.size(), 2u);
EXPECT_EQ(RetEmb.size(), 2u);
- EXPECT_TRUE(AddEmb.approximatelyEquals(Embedding(2, 25.5)));
- EXPECT_TRUE(RetEmb.approximatelyEquals(Embedding(2, 32.6)));
+ EXPECT_TRUE(AddEmb.approximatelyEquals(Embedding(2, 25.9)));
+ EXPECT_TRUE(RetEmb.approximatelyEquals(Embedding(2, 33.1)));
}
TEST_F(IR2VecTestFixture, GetBBVector_Symbolic) {
@@ -387,9 +387,9 @@ TEST_F(IR2VecTestFixture, GetBBVector_Symbolic) {
const auto &BBVec = Emb->getBBVector(*BB);
EXPECT_EQ(BBVec.size(), 2u);
- // BB vector should be sum of add and ret: {25.5, 25.5} + {15.5, 15.5} =
- // {41.0, 41.0}
- EXPECT_TRUE(BBVec.approximatelyEquals(Embedding(2, 41.0)));
+ // BB vector should be sum of add and ret: {25.9, 25.9} + {15.7, 15.7} =
+ // {41.6, 41.6}
+ EXPECT_TRUE(BBVec.approximatelyEquals(Embedding(2, 41.6)));
}
TEST_F(IR2VecTestFixture, GetBBVector_FlowAware) {
@@ -399,9 +399,9 @@ TEST_F(IR2VecTestFixture, GetBBVector_FlowAware) {
const auto &BBVec = Emb->getBBVector(*BB);
EXPECT_EQ(BBVec.size(), 2u);
- // BB vector should be sum of add and ret: {25.5, 25.5} + {32.6, 32.6} =
- // {58.1, 58.1}
- EXPECT_TRUE(BBVec.approximatelyEquals(Embedding(2, 58.1)));
+ // BB vector should be sum of add and ret: {25.9, 25.9} + {33.1, 33.1} =
+ // {59.0, 59.0}
+ EXPECT_TRUE(BBVec.approximatelyEquals(Embedding(2, 59.0)));
}
TEST_F(IR2VecTestFixture, GetFunctionVector_Symbolic) {
@@ -412,8 +412,8 @@ TEST_F(IR2VecTestFixture, GetFunctionVector_Symbolic) {
EXPECT_EQ(FuncVec.size(), 2u);
- // Function vector should match BB vector (only one BB): {41.0, 41.0}
- EXPECT_TRUE(FuncVec.approximatelyEquals(Embedding(2, 41.0)));
+ // Function vector should match BB vector (only one BB): {41.6, 41.6}
+ EXPECT_TRUE(FuncVec.approximatelyEquals(Embedding(2, 41.6)));
}
TEST_F(IR2VecTestFixture, GetFunctionVector_FlowAware) {
@@ -423,8 +423,8 @@ TEST_F(IR2VecTestFixture, GetFunctionVector_FlowAware) {
const auto &FuncVec = Emb->getFunctionVector();
EXPECT_EQ(FuncVec.size(), 2u);
- // Function vector should match BB vector (only one BB): {58.1, 58.1}
- EXPECT_TRUE(FuncVec.approximatelyEquals(Embedding(2, 58.1)));
+ // Function vector should match BB vector (only one BB): {59.0, 59.0}
+ EXPECT_TRUE(FuncVec.approximatelyEquals(Embedding(2, 59.0)));
}
TEST_F(IR2VecTestFixture, MultipleComputeEmbeddingsConsistency_Symbolic) {
@@ -611,7 +611,7 @@ TEST(IR2VecVocabularyTest, NumericIDMapInvalidInputs) {
TEST(IR2VecVocabularyTest, StringKeyGeneration) {
EXPECT_EQ(Vocabulary::getStringKey(0), "Ret");
- EXPECT_EQ(Vocabulary::getStringKey(12), "Add");
+ EXPECT_EQ(Vocabulary::getStringKey(13), "Add");
#define EXPECT_OPCODE(NUM, OPCODE, CLASS) \
EXPECT_EQ(Vocabulary::getStringKey(Vocabulary::getIndex(NUM)), \
@@ -1041,7 +1041,8 @@ class VocabFileTest : public ::testing::Test {
// Add all required opcodes
const char *Opcodes[] = {"Ret",
- "Br",
+ "UncondBr",
+ "CondBr",
"Switch",
"IndirectBr",
"Invoke",
diff --git a/mlir/lib/Target/LLVMIR/ModuleImport.cpp b/mlir/lib/Target/LLVMIR/ModuleImport.cpp
index 2fbf0ce38f6cc..f161fca6d6ff4 100644
--- a/mlir/lib/Target/LLVMIR/ModuleImport.cpp
+++ b/mlir/lib/Target/LLVMIR/ModuleImport.cpp
@@ -2254,8 +2254,20 @@ ModuleImport::convertAsmInlineOperandAttrs(const llvm::CallBase &llvmCall) {
LogicalResult ModuleImport::convertInstruction(llvm::Instruction *inst) {
// Convert all instructions that do not provide an MLIR builder.
Location loc = translateLoc(inst->getDebugLoc());
- if (inst->getOpcode() == llvm::Instruction::Br) {
- auto *brInst = cast<llvm::BranchInst>(inst);
+ if (inst->getOpcode() == llvm::Instruction::UncondBr) {
+ auto *brInst = cast<llvm::UncondBrInst>(inst);
+
+ llvm::BasicBlock *succ = brInst->getSuccessor(0);
+ SmallVector<Value> blockArgs;
+ if (failed(convertBranchArgs(brInst, succ, blockArgs)))
+ return failure();
+
+ auto brOp = LLVM::BrOp::create(builder, loc, blockArgs, lookupBlock(succ));
+ mapNoResultOp(inst, brOp);
+ return success();
+ }
+ if (inst->getOpcode() == llvm::Instruction::CondBr) {
+ auto *brInst = cast<llvm::CondBrInst>(inst);
SmallVector<Block *> succBlocks;
SmallVector<SmallVector<Value>> succBlockArgs;
@@ -2268,12 +2280,6 @@ LogicalResult ModuleImport::convertInstruction(llvm::Instruction *inst) {
succBlockArgs.push_back(blockArgs);
}
- if (!brInst->isConditional()) {
- auto brOp = LLVM::BrOp::create(builder, loc, succBlockArgs.front(),
- succBlocks.front());
- mapNoResultOp(inst, brOp);
- return success();
- }
FailureOr<Value> condition = convertValue(brInst->getCondition());
if (failed(condition))
return failure();
>From 70f5fa8e445cafe83699cedf6806bd7f813f98a3 Mon Sep 17 00:00:00 2001
From: Alexis Engelke <engelke at in.tum.de>
Date: Mon, 2 Mar 2026 08:58:40 +0000
Subject: [PATCH 2/8] feedback
---
llvm/include/llvm/IR/Instructions.h | 21 ++++++++-------
.../SelectionDAG/SelectionDAGBuilder.cpp | 2 --
llvm/lib/CodeGen/TypePromotion.cpp | 1 -
llvm/lib/IR/Instructions.cpp | 27 +++++++------------
llvm/lib/Transforms/Utils/SimplifyCFG.cpp | 8 +++---
5 files changed, 25 insertions(+), 34 deletions(-)
diff --git a/llvm/include/llvm/IR/Instructions.h b/llvm/include/llvm/IR/Instructions.h
index 8f1014594a7b8..cb8a8d1daa3b7 100644
--- a/llvm/include/llvm/IR/Instructions.h
+++ b/llvm/include/llvm/IR/Instructions.h
@@ -3159,8 +3159,10 @@ DEFINE_TRANSPARENT_OPERAND_ACCESSORS(BranchInst, Value)
/// Unconditional Branch instruction.
///
class UncondBrInst : public BranchInst {
- UncondBrInst(const UncondBrInst &BI, AllocInfo AllocInfo);
- LLVM_ABI explicit UncondBrInst(BasicBlock *IfTrue, AllocInfo AllocInfo,
+ constexpr static IntrusiveOperandsAllocMarker AllocMarker{1};
+
+ UncondBrInst(const UncondBrInst &BI);
+ LLVM_ABI explicit UncondBrInst(BasicBlock *IfTrue,
InsertPosition InsertBefore);
protected:
@@ -3172,8 +3174,7 @@ class UncondBrInst : public BranchInst {
public:
static UncondBrInst *Create(BasicBlock *IfTrue,
InsertPosition InsertBefore = nullptr) {
- IntrusiveOperandsAllocMarker AllocMarker{1};
- return new (AllocMarker) UncondBrInst(IfTrue, AllocMarker, InsertBefore);
+ return new (AllocMarker) UncondBrInst(IfTrue, InsertBefore);
}
/// Transparently provide more efficient getOperand methods.
@@ -3231,12 +3232,14 @@ DEFINE_TRANSPARENT_OPERAND_ACCESSORS(UncondBrInst, Value)
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------------
-/// Conditional or Unconditional Branch instruction.
+/// Conditional Branch instruction.
///
class CondBrInst : public BranchInst {
- CondBrInst(const CondBrInst &BI, AllocInfo AllocInfo);
+ constexpr static IntrusiveOperandsAllocMarker AllocMarker{3};
+
+ CondBrInst(const CondBrInst &BI);
LLVM_ABI CondBrInst(BasicBlock *IfTrue, BasicBlock *IfFalse, Value *Cond,
- AllocInfo AllocInfo, InsertPosition InsertBefore);
+ InsertPosition InsertBefore);
void AssertOK();
@@ -3255,9 +3258,7 @@ class CondBrInst : public BranchInst {
static CondBrInst *Create(BasicBlock *IfTrue, BasicBlock *IfFalse,
Value *Cond,
InsertPosition InsertBefore = nullptr) {
- IntrusiveOperandsAllocMarker AllocMarker{3};
- return new (AllocMarker)
- CondBrInst(IfTrue, IfFalse, Cond, AllocMarker, InsertBefore);
+ return new (AllocMarker) CondBrInst(IfTrue, IfFalse, Cond, InsertBefore);
}
/// Transparently provide more efficient getOperand methods.
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index 89a314444b0f5..105e062225f24 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -2805,7 +2805,6 @@ SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases) {
void SelectionDAGBuilder::visitUncondBr(const UncondBrInst &I) {
MachineBasicBlock *BrMBB = FuncInfo.MBB;
- // Update machine-CFG edges.
MachineBasicBlock *Succ0MBB = FuncInfo.getMBB(I.getSuccessor(0));
// Update machine-CFG edges.
@@ -2827,7 +2826,6 @@ void SelectionDAGBuilder::visitUncondBr(const UncondBrInst &I) {
void SelectionDAGBuilder::visitCondBr(const CondBrInst &I) {
MachineBasicBlock *BrMBB = FuncInfo.MBB;
- // Update machine-CFG edges.
MachineBasicBlock *Succ0MBB = FuncInfo.getMBB(I.getSuccessor(0));
// If this condition is one of the special cases we handle, do special stuff
diff --git a/llvm/lib/CodeGen/TypePromotion.cpp b/llvm/lib/CodeGen/TypePromotion.cpp
index a6014ca851fae..77f82b3851904 100644
--- a/llvm/lib/CodeGen/TypePromotion.cpp
+++ b/llvm/lib/CodeGen/TypePromotion.cpp
@@ -732,7 +732,6 @@ bool TypePromotionImpl::isSupportedValue(Value *V) {
!GenerateSignBits(I);
case Instruction::GetElementPtr:
case Instruction::Store:
- case Instruction::UncondBr:
case Instruction::CondBr:
case Instruction::Switch:
return true;
diff --git a/llvm/lib/IR/Instructions.cpp b/llvm/lib/IR/Instructions.cpp
index 3c3b8e1d3637c..fe27959445d38 100644
--- a/llvm/lib/IR/Instructions.cpp
+++ b/llvm/lib/IR/Instructions.cpp
@@ -1189,19 +1189,16 @@ UnreachableInst::UnreachableInst(LLVMContext &Context,
// UncondBrInst Implementation
//===----------------------------------------------------------------------===//
-UncondBrInst::UncondBrInst(BasicBlock *IfTrue, AllocInfo AllocInfo,
- InsertPosition InsertBefore)
+UncondBrInst::UncondBrInst(BasicBlock *IfTrue, InsertPosition InsertBefore)
: BranchInst(Type::getVoidTy(IfTrue->getContext()), Instruction::UncondBr,
- AllocInfo, InsertBefore) {
+ AllocMarker, InsertBefore) {
assert(IfTrue && "Branch destination may not be null!");
Op<-1>() = IfTrue;
}
-UncondBrInst::UncondBrInst(const UncondBrInst &BI, AllocInfo AllocInfo)
+UncondBrInst::UncondBrInst(const UncondBrInst &BI)
: BranchInst(Type::getVoidTy(BI.getContext()), Instruction::UncondBr,
- AllocInfo) {
- assert(getNumOperands() == BI.getNumOperands() &&
- "Wrong number of operands allocated");
+ AllocMarker) {
Op<-1>() = BI.Op<-1>();
SubclassOptionalData = BI.SubclassOptionalData;
}
@@ -1216,9 +1213,9 @@ void CondBrInst::AssertOK() {
}
CondBrInst::CondBrInst(BasicBlock *IfTrue, BasicBlock *IfFalse, Value *Cond,
- AllocInfo AllocInfo, InsertPosition InsertBefore)
+ InsertPosition InsertBefore)
: BranchInst(Type::getVoidTy(IfTrue->getContext()), Instruction::CondBr,
- AllocInfo, InsertBefore) {
+ AllocMarker, InsertBefore) {
// Assign in order of operand index to make use-list order predictable.
Op<-3>() = Cond;
Op<-2>() = IfFalse;
@@ -1228,11 +1225,9 @@ CondBrInst::CondBrInst(BasicBlock *IfTrue, BasicBlock *IfFalse, Value *Cond,
#endif
}
-CondBrInst::CondBrInst(const CondBrInst &BI, AllocInfo AllocInfo)
+CondBrInst::CondBrInst(const CondBrInst &BI)
: BranchInst(Type::getVoidTy(BI.getContext()), Instruction::CondBr,
- AllocInfo) {
- assert(getNumOperands() == BI.getNumOperands() &&
- "Wrong number of operands allocated");
+ AllocMarker) {
// Assign in order of operand index to make use-list order predictable.
Op<-3>() = BI.Op<-3>();
Op<-2>() = BI.Op<-2>();
@@ -4507,13 +4502,11 @@ ReturnInst *ReturnInst::cloneImpl() const {
}
UncondBrInst *UncondBrInst::cloneImpl() const {
- IntrusiveOperandsAllocMarker AllocMarker{getNumOperands()};
- return new (AllocMarker) UncondBrInst(*this, AllocMarker);
+ return new (AllocMarker) UncondBrInst(*this);
}
CondBrInst *CondBrInst::cloneImpl() const {
- IntrusiveOperandsAllocMarker AllocMarker{getNumOperands()};
- return new (AllocMarker) CondBrInst(*this, AllocMarker);
+ return new (AllocMarker) CondBrInst(*this);
}
SwitchInst *SwitchInst::cloneImpl() const { return new SwitchInst(*this); }
diff --git a/llvm/lib/Transforms/Utils/SimplifyCFG.cpp b/llvm/lib/Transforms/Utils/SimplifyCFG.cpp
index e104fd563c331..036ba9fc30a15 100644
--- a/llvm/lib/Transforms/Utils/SimplifyCFG.cpp
+++ b/llvm/lib/Transforms/Utils/SimplifyCFG.cpp
@@ -295,8 +295,8 @@ class SimplifyCFGOpt {
bool simplifySwitch(SwitchInst *SI, IRBuilder<> &Builder);
bool simplifyDuplicateSwitchArms(SwitchInst *SI, DomTreeUpdater *DTU);
bool simplifyIndirectBr(IndirectBrInst *IBI);
- bool simplifyUncondBranch(BranchInst *BI, IRBuilder<> &Builder);
- bool simplifyCondBranch(BranchInst *BI, IRBuilder<> &Builder);
+ bool simplifyUncondBranch(UncondBrInst *BI, IRBuilder<> &Builder);
+ bool simplifyCondBranch(CondBrInst *BI, IRBuilder<> &Builder);
bool foldCondBranchOnValueKnownInPredecessor(BranchInst *BI);
bool tryToSimplifyUncondBranchWithICmpInIt(ICmpInst *ICI,
@@ -8369,7 +8369,7 @@ static bool tryToMergeLandingPad(LandingPadInst *LPad, BranchInst *BI,
return false;
}
-bool SimplifyCFGOpt::simplifyUncondBranch(BranchInst *BI,
+bool SimplifyCFGOpt::simplifyUncondBranch(UncondBrInst *BI,
IRBuilder<> &Builder) {
BasicBlock *BB = BI->getParent();
BasicBlock *Succ = BI->getSuccessor(0);
@@ -8524,7 +8524,7 @@ static bool mergeNestedCondBranch(BranchInst *BI, DomTreeUpdater *DTU) {
return true;
}
-bool SimplifyCFGOpt::simplifyCondBranch(BranchInst *BI, IRBuilder<> &Builder) {
+bool SimplifyCFGOpt::simplifyCondBranch(CondBrInst *BI, IRBuilder<> &Builder) {
assert(
!isa<ConstantInt>(BI->getCondition()) &&
BI->getSuccessor(0) != BI->getSuccessor(1) &&
>From b63b9f33ee9b376e983adf0b7508bf8a06cdb713 Mon Sep 17 00:00:00 2001
From: Alexis Engelke <engelke at in.tum.de>
Date: Mon, 2 Mar 2026 09:04:04 +0000
Subject: [PATCH 3/8] Release Notes
---
llvm/docs/ReleaseNotes.md | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md
index 2e0c5c5cb9370..61090e89a5c81 100644
--- a/llvm/docs/ReleaseNotes.md
+++ b/llvm/docs/ReleaseNotes.md
@@ -83,6 +83,9 @@ Changes to LLVM infrastructure
* Removed `bugpoint`. Usage has been replaced by `llvm-reduce` and
`llvm/utils/reduce_pipeline.py`.
+* The ``Br`` opcode got split into two opcodes separating unconditional
+ (``UncondBr``) and conditional (``CondBr``) branches.
+
Changes to building LLVM
------------------------
@@ -182,6 +185,8 @@ Changes to the Python bindings
Changes to the C API
--------------------
+* Replaced opcode ``LLVMBr`` with ``LLVMUncondBr`` and ``LLVMCondBr``.
+
Changes to the CodeGen infrastructure
-------------------------------------
>From ac006e2146766363b3ad69b787bc9476ae3a64f5 Mon Sep 17 00:00:00 2001
From: Alexis Engelke <engelke at in.tum.de>
Date: Mon, 2 Mar 2026 12:07:27 +0000
Subject: [PATCH 4/8] Fix LLDB
---
lldb/source/Expression/IRInterpreter.cpp | 48 ++++++++++++------------
1 file changed, 23 insertions(+), 25 deletions(-)
diff --git a/lldb/source/Expression/IRInterpreter.cpp b/lldb/source/Expression/IRInterpreter.cpp
index 5ca64843d5900..612b72d6fc463 100644
--- a/lldb/source/Expression/IRInterpreter.cpp
+++ b/lldb/source/Expression/IRInterpreter.cpp
@@ -549,7 +549,8 @@ bool IRInterpreter::CanInterpret(llvm::Module &module, llvm::Function &function,
case Instruction::Add:
case Instruction::Alloca:
case Instruction::BitCast:
- case Instruction::Br:
+ case Instruction::UncondBr:
+ case Instruction::CondBr:
case Instruction::PHI:
break;
case Instruction::Call: {
@@ -989,36 +990,33 @@ bool IRInterpreter::Interpret(llvm::Module &module, llvm::Function &function,
frame.AssignValue(inst, S_signextend, module);
} break;
- case Instruction::Br: {
- const BranchInst *br_inst = cast<BranchInst>(inst);
+ case Instruction::UncondBr:
+ frame.Jump(cast<UncondBrInst>(inst)->getSuccessor());
+ if (log) {
+ LLDB_LOGF(log, "Interpreted an UncondBrInst");
+ }
+ continue;
+ case Instruction::CondBr:
+ const CondBrInst *br_inst = cast<CondBrInst>(inst);
- if (br_inst->isConditional()) {
- Value *condition = br_inst->getCondition();
+ Value *condition = br_inst->getCondition();
- lldb_private::Scalar C;
+ lldb_private::Scalar C;
- if (!frame.EvaluateValue(C, condition, module)) {
- LLDB_LOGF(log, "Couldn't evaluate %s", PrintValue(condition).c_str());
- error = lldb_private::Status::FromErrorString(bad_value_error);
- return false;
- }
-
- if (!C.IsZero())
- frame.Jump(br_inst->getSuccessor(0));
- else
- frame.Jump(br_inst->getSuccessor(1));
+ if (!frame.EvaluateValue(C, condition, module)) {
+ LLDB_LOGF(log, "Couldn't evaluate %s", PrintValue(condition).c_str());
+ error = lldb_private::Status::FromErrorString(bad_value_error);
+ return false;
+ }
- if (log) {
- LLDB_LOGF(log, "Interpreted a BrInst with a condition");
- LLDB_LOGF(log, " cond : %s",
- frame.SummarizeValue(condition).c_str());
- }
- } else {
+ if (!C.IsZero())
frame.Jump(br_inst->getSuccessor(0));
+ else
+ frame.Jump(br_inst->getSuccessor(1));
- if (log) {
- LLDB_LOGF(log, "Interpreted a BrInst with no condition");
- }
+ if (log) {
+ LLDB_LOGF(log, "Interpreted a CondBrInst");
+ LLDB_LOGF(log, " cond : %s", frame.SummarizeValue(condition).c_str());
}
}
continue;
>From 738792efa9728506d64c367a6b6dfd0cf23a07a2 Mon Sep 17 00:00:00 2001
From: Alexis Engelke <engelke at in.tum.de>
Date: Mon, 2 Mar 2026 12:34:31 +0000
Subject: [PATCH 5/8] Fix LLDB for real
---
lldb/source/Expression/IRInterpreter.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/lldb/source/Expression/IRInterpreter.cpp b/lldb/source/Expression/IRInterpreter.cpp
index 612b72d6fc463..9b3936d065cba 100644
--- a/lldb/source/Expression/IRInterpreter.cpp
+++ b/lldb/source/Expression/IRInterpreter.cpp
@@ -996,7 +996,7 @@ bool IRInterpreter::Interpret(llvm::Module &module, llvm::Function &function,
LLDB_LOGF(log, "Interpreted an UncondBrInst");
}
continue;
- case Instruction::CondBr:
+ case Instruction::CondBr: {
const CondBrInst *br_inst = cast<CondBrInst>(inst);
Value *condition = br_inst->getCondition();
>From b9f31adc71615932da61486fbd0f58b7e9d7d876 Mon Sep 17 00:00:00 2001
From: Alexis Engelke <engelke at in.tum.de>
Date: Mon, 2 Mar 2026 14:16:45 +0000
Subject: [PATCH 6/8] ReleaseNotes feedback
---
llvm/docs/ReleaseNotes.md | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md
index 61090e89a5c81..c5492dfbcba28 100644
--- a/llvm/docs/ReleaseNotes.md
+++ b/llvm/docs/ReleaseNotes.md
@@ -83,7 +83,7 @@ Changes to LLVM infrastructure
* Removed `bugpoint`. Usage has been replaced by `llvm-reduce` and
`llvm/utils/reduce_pipeline.py`.
-* The ``Br`` opcode got split into two opcodes separating unconditional
+* The ``Br`` opcode was split into two opcodes separating unconditional
(``UncondBr``) and conditional (``CondBr``) branches.
Changes to building LLVM
>From 354150aed6f43a2eaa1ebde998304eb67da46a0a Mon Sep 17 00:00:00 2001
From: Alexis Engelke <engelke at in.tum.de>
Date: Sat, 7 Mar 2026 09:36:27 +0000
Subject: [PATCH 7/8] CondBrInst operand order
---
llvm/include/llvm/IR/Instructions.h | 10 +++++-----
llvm/lib/IR/Instructions.cpp | 2 +-
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/llvm/include/llvm/IR/Instructions.h b/llvm/include/llvm/IR/Instructions.h
index cb8a8d1daa3b7..f4d7ee9ecb52d 100644
--- a/llvm/include/llvm/IR/Instructions.h
+++ b/llvm/include/llvm/IR/Instructions.h
@@ -3238,7 +3238,7 @@ class CondBrInst : public BranchInst {
constexpr static IntrusiveOperandsAllocMarker AllocMarker{3};
CondBrInst(const CondBrInst &BI);
- LLVM_ABI CondBrInst(BasicBlock *IfTrue, BasicBlock *IfFalse, Value *Cond,
+ LLVM_ABI CondBrInst(Value *Cond, BasicBlock *IfTrue, BasicBlock *IfFalse,
InsertPosition InsertBefore);
void AssertOK();
@@ -3255,10 +3255,10 @@ class CondBrInst : public BranchInst {
using BranchInst::isUnconditional;
public:
- static CondBrInst *Create(BasicBlock *IfTrue, BasicBlock *IfFalse,
- Value *Cond,
+ static CondBrInst *Create(Value *Cond, BasicBlock *IfTrue,
+ BasicBlock *IfFalse,
InsertPosition InsertBefore = nullptr) {
- return new (AllocMarker) CondBrInst(IfTrue, IfFalse, Cond, InsertBefore);
+ return new (AllocMarker) CondBrInst(Cond, IfTrue, IfFalse, InsertBefore);
}
/// Transparently provide more efficient getOperand methods.
@@ -3323,7 +3323,7 @@ inline BranchInst *BranchInst::Create(BasicBlock *IfTrue,
inline BranchInst *BranchInst::Create(BasicBlock *IfTrue, BasicBlock *IfFalse,
Value *Cond,
InsertPosition InsertBefore) {
- return CondBrInst::Create(IfTrue, IfFalse, Cond, InsertBefore);
+ return CondBrInst::Create(Cond, IfTrue, IfFalse, InsertBefore);
}
inline bool BranchInst::isConditional() const { return isa<CondBrInst>(this); }
diff --git a/llvm/lib/IR/Instructions.cpp b/llvm/lib/IR/Instructions.cpp
index fe27959445d38..4c00ee29ac782 100644
--- a/llvm/lib/IR/Instructions.cpp
+++ b/llvm/lib/IR/Instructions.cpp
@@ -1212,7 +1212,7 @@ void CondBrInst::AssertOK() {
"May only branch on boolean predicates!");
}
-CondBrInst::CondBrInst(BasicBlock *IfTrue, BasicBlock *IfFalse, Value *Cond,
+CondBrInst::CondBrInst(Value *Cond, BasicBlock *IfTrue, BasicBlock *IfFalse,
InsertPosition InsertBefore)
: BranchInst(Type::getVoidTy(IfTrue->getContext()), Instruction::CondBr,
AllocMarker, InsertBefore) {
>From 26b8b44bc11a1c908a20ac0b846ba984dfc4d24c Mon Sep 17 00:00:00 2001
From: Alexis Engelke <engelke at in.tum.de>
Date: Sat, 7 Mar 2026 09:38:56 +0000
Subject: [PATCH 8/8] dyn_cast + remove unnecessary return
---
llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 2 --
mlir/lib/Target/LLVMIR/ModuleImport.cpp | 10 +++-------
2 files changed, 3 insertions(+), 9 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index 8b242d3f5d570..cef77dc1d3f60 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -2819,8 +2819,6 @@ void SelectionDAGBuilder::visitUncondBr(const UncondBrInst &I) {
setValue(&I, Br);
DAG.setRoot(Br);
}
-
- return;
}
void SelectionDAGBuilder::visitCondBr(const CondBrInst &I) {
diff --git a/mlir/lib/Target/LLVMIR/ModuleImport.cpp b/mlir/lib/Target/LLVMIR/ModuleImport.cpp
index f161fca6d6ff4..398a11eac6460 100644
--- a/mlir/lib/Target/LLVMIR/ModuleImport.cpp
+++ b/mlir/lib/Target/LLVMIR/ModuleImport.cpp
@@ -2254,10 +2254,8 @@ ModuleImport::convertAsmInlineOperandAttrs(const llvm::CallBase &llvmCall) {
LogicalResult ModuleImport::convertInstruction(llvm::Instruction *inst) {
// Convert all instructions that do not provide an MLIR builder.
Location loc = translateLoc(inst->getDebugLoc());
- if (inst->getOpcode() == llvm::Instruction::UncondBr) {
- auto *brInst = cast<llvm::UncondBrInst>(inst);
-
- llvm::BasicBlock *succ = brInst->getSuccessor(0);
+ if (auto *brInst = dyn_cast<llvm::UncondBrInst>(inst)) {
+ llvm::BasicBlock *succ = brInst->getSuccessor();
SmallVector<Value> blockArgs;
if (failed(convertBranchArgs(brInst, succ, blockArgs)))
return failure();
@@ -2266,9 +2264,7 @@ LogicalResult ModuleImport::convertInstruction(llvm::Instruction *inst) {
mapNoResultOp(inst, brOp);
return success();
}
- if (inst->getOpcode() == llvm::Instruction::CondBr) {
- auto *brInst = cast<llvm::CondBrInst>(inst);
-
+ if (auto *brInst = dyn_cast<llvm::CondBrInst>(inst)) {
SmallVector<Block *> succBlocks;
SmallVector<SmallVector<Value>> succBlockArgs;
for (auto i : llvm::seq<unsigned>(0, brInst->getNumSuccessors())) {
More information about the llvm-commits
mailing list