[llvm] [DAG] isKnownNeverZero: Add DemandedElts handling for ROTL/ROTR/BITREVERSE/BSWAP/CTPOP/ABS (PR #184033)
Ayush Kumar Gaur via llvm-commits
llvm-commits at lists.llvm.org
Sat Mar 7 00:51:49 PST 2026
https://github.com/Ayush3941 updated https://github.com/llvm/llvm-project/pull/184033
>From 2859336292085d42da26be9ecc5fb898de5bb14a Mon Sep 17 00:00:00 2001
From: Ayush3941 <ayushkgaur1 at gmail.com>
Date: Sun, 1 Mar 2026 14:54:12 -0500
Subject: [PATCH 1/4] [DAG] isKnownNeverZero: Add DemandedElts handling for
ROTL/ROTR/BITREVERSE/BSWAP/CTPOP/ABS
---
.../lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 2 +-
.../X86/known-never-zero-demanded-elts.ll | 78 +++++++++++++++++++
2 files changed, 79 insertions(+), 1 deletion(-)
create mode 100644 llvm/test/CodeGen/X86/known-never-zero-demanded-elts.ll
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 31a83dd6e0ec0..c5750b36dc629 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -6290,7 +6290,7 @@ bool SelectionDAG::isKnownNeverZero(SDValue Op, const APInt &DemandedElts,
case ISD::BSWAP:
case ISD::CTPOP:
case ISD::ABS:
- return isKnownNeverZero(Op.getOperand(0), Depth + 1);
+ return isKnownNeverZero(Op.getOperand(0), DemandedElts, Depth + 1);
case ISD::SRA:
case ISD::SRL: {
diff --git a/llvm/test/CodeGen/X86/known-never-zero-demanded-elts.ll b/llvm/test/CodeGen/X86/known-never-zero-demanded-elts.ll
new file mode 100644
index 0000000000000..97725d0e4dddd
--- /dev/null
+++ b/llvm/test/CodeGen/X86/known-never-zero-demanded-elts.ll
@@ -0,0 +1,78 @@
+; RUN: llc -O2 -mtriple=x86_64-unknown-linux-gnu %s -o - | FileCheck %s
+
+; Helper: build vector with lane0 set, other lanes undef.
+
+declare <4 x i8> @llvm.ctpop.v4i8(<4 x i8>)
+declare <4 x i16> @llvm.bswap.v4i16(<4 x i16>)
+declare <4 x i8> @llvm.bitreverse.v4i8(<4 x i8>)
+declare <4 x i8> @llvm.fshl.v4i8(<4 x i8>, <4 x i8>, <4 x i8>)
+declare <4 x i8> @llvm.fshr.v4i8(<4 x i8>, <4 x i8>, <4 x i8>)
+declare <4 x i8> @llvm.abs.v4i8(<4 x i8>, i1)
+
+define i1 @ctpop_lane0_nonzero() {
+; CHECK-LABEL: ctpop_lane0_nonzero:
+; CHECK: mov{{.*}}1
+; CHECK: ret
+ %v0 = insertelement <4 x i8> undef, i8 8, i64 0 ; lane0 = 8 (non-zero)
+ %w = call <4 x i8> @llvm.ctpop.v4i8(<4 x i8> %v0) ; ctpop(8)=1 -> non-zero
+ %e0 = extractelement <4 x i8> %w, i64 0
+ %cmp = icmp ne i8 %e0, 0
+ ret i1 %cmp
+}
+
+define i1 @bswap_lane0_nonzero() {
+; CHECK-LABEL: bswap_lane0_nonzero:
+; CHECK: mov{{.*}}1
+; CHECK: ret
+ %v0 = insertelement <4 x i16> undef, i16 1, i64 0 ; lane0 = 1
+ %w = call <4 x i16> @llvm.bswap.v4i16(<4 x i16> %v0) ; bswap(1)=256 -> non-zero
+ %e0 = extractelement <4 x i16> %w, i64 0
+ %cmp = icmp ne i16 %e0, 0
+ ret i1 %cmp
+}
+
+define i1 @bitreverse_lane0_nonzero() {
+; CHECK-LABEL: bitreverse_lane0_nonzero:
+; CHECK: mov{{.*}}1
+; CHECK: ret
+ %v0 = insertelement <4 x i8> undef, i8 1, i64 0 ; lane0 = 1
+ %w = call <4 x i8> @llvm.bitreverse.v4i8(<4 x i8> %v0) ; bitreverse(1)=0x80 -> non-zero
+ %e0 = extractelement <4 x i8> %w, i64 0
+ %cmp = icmp ne i8 %e0, 0
+ ret i1 %cmp
+}
+
+define i1 @rotl_lane0_nonzero() {
+; CHECK-LABEL: rotl_lane0_nonzero:
+; CHECK: mov{{.*}}1
+; CHECK: ret
+ %x = insertelement <4 x i8> undef, i8 2, i64 0 ; lane0 = 2 (non-zero)
+ %k = insertelement <4 x i8> undef, i8 1, i64 0 ; rotate by 1
+ %w = call <4 x i8> @llvm.fshl.v4i8(<4 x i8> %x, <4 x i8> %x, <4 x i8> %k)
+ %e0 = extractelement <4 x i8> %w, i64 0
+ %cmp = icmp ne i8 %e0, 0
+ ret i1 %cmp
+}
+
+define i1 @rotr_lane0_nonzero() {
+; CHECK-LABEL: rotr_lane0_nonzero:
+; CHECK: mov{{.*}}1
+; CHECK: ret
+ %x = insertelement <4 x i8> undef, i8 2, i64 0
+ %k = insertelement <4 x i8> undef, i8 1, i64 0
+ %w = call <4 x i8> @llvm.fshr.v4i8(<4 x i8> %x, <4 x i8> %x, <4 x i8> %k)
+ %e0 = extractelement <4 x i8> %w, i64 0
+ %cmp = icmp ne i8 %e0, 0
+ ret i1 %cmp
+}
+
+define i1 @abs_lane0_nonzero() {
+; CHECK-LABEL: abs_lane0_nonzero:
+; CHECK: mov{{.*}}1
+; CHECK: ret
+ %v0 = insertelement <4 x i8> undef, i8 -2, i64 0 ; lane0 = -2 (non-zero)
+ %w = call <4 x i8> @llvm.abs.v4i8(<4 x i8> %v0, i1 false)
+ %e0 = extractelement <4 x i8> %w, i64 0
+ %cmp = icmp ne i8 %e0, 0
+ ret i1 %cmp
+}
\ No newline at end of file
>From e1022800edd244b75efb32b4dae5636afb7462d6 Mon Sep 17 00:00:00 2001
From: Ayush3941 <ayushkgaur1 at gmail.com>
Date: Sun, 1 Mar 2026 15:07:07 -0500
Subject: [PATCH 2/4] [DAG] isKnownNeverZero: Add DemandedElts handling for
ROTL/ROTR/BITREVERSE/BSWAP/CTPOP/ABS v2
---
.../X86/known-never-zero-demanded-elts.ll | 28 +++++++++----------
1 file changed, 14 insertions(+), 14 deletions(-)
diff --git a/llvm/test/CodeGen/X86/known-never-zero-demanded-elts.ll b/llvm/test/CodeGen/X86/known-never-zero-demanded-elts.ll
index 97725d0e4dddd..34942bf8d9ab5 100644
--- a/llvm/test/CodeGen/X86/known-never-zero-demanded-elts.ll
+++ b/llvm/test/CodeGen/X86/known-never-zero-demanded-elts.ll
@@ -1,20 +1,20 @@
; RUN: llc -O2 -mtriple=x86_64-unknown-linux-gnu %s -o - | FileCheck %s
-; Helper: build vector with lane0 set, other lanes undef.
+; Helper: build vector with lane0 set, other lanes poison.
declare <4 x i8> @llvm.ctpop.v4i8(<4 x i8>)
declare <4 x i16> @llvm.bswap.v4i16(<4 x i16>)
declare <4 x i8> @llvm.bitreverse.v4i8(<4 x i8>)
declare <4 x i8> @llvm.fshl.v4i8(<4 x i8>, <4 x i8>, <4 x i8>)
declare <4 x i8> @llvm.fshr.v4i8(<4 x i8>, <4 x i8>, <4 x i8>)
-declare <4 x i8> @llvm.abs.v4i8(<4 x i8>, i1)
+declare <4 x i8> @llvm.abs.v4i8(<4 x i8>, i1)
define i1 @ctpop_lane0_nonzero() {
; CHECK-LABEL: ctpop_lane0_nonzero:
; CHECK: mov{{.*}}1
; CHECK: ret
- %v0 = insertelement <4 x i8> undef, i8 8, i64 0 ; lane0 = 8 (non-zero)
- %w = call <4 x i8> @llvm.ctpop.v4i8(<4 x i8> %v0) ; ctpop(8)=1 -> non-zero
+ %v0 = insertelement <4 x i8> poison, i8 8, i64 0
+ %w = call <4 x i8> @llvm.ctpop.v4i8(<4 x i8> %v0)
%e0 = extractelement <4 x i8> %w, i64 0
%cmp = icmp ne i8 %e0, 0
ret i1 %cmp
@@ -24,8 +24,8 @@ define i1 @bswap_lane0_nonzero() {
; CHECK-LABEL: bswap_lane0_nonzero:
; CHECK: mov{{.*}}1
; CHECK: ret
- %v0 = insertelement <4 x i16> undef, i16 1, i64 0 ; lane0 = 1
- %w = call <4 x i16> @llvm.bswap.v4i16(<4 x i16> %v0) ; bswap(1)=256 -> non-zero
+ %v0 = insertelement <4 x i16> poison, i16 1, i64 0
+ %w = call <4 x i16> @llvm.bswap.v4i16(<4 x i16> %v0)
%e0 = extractelement <4 x i16> %w, i64 0
%cmp = icmp ne i16 %e0, 0
ret i1 %cmp
@@ -35,8 +35,8 @@ define i1 @bitreverse_lane0_nonzero() {
; CHECK-LABEL: bitreverse_lane0_nonzero:
; CHECK: mov{{.*}}1
; CHECK: ret
- %v0 = insertelement <4 x i8> undef, i8 1, i64 0 ; lane0 = 1
- %w = call <4 x i8> @llvm.bitreverse.v4i8(<4 x i8> %v0) ; bitreverse(1)=0x80 -> non-zero
+ %v0 = insertelement <4 x i8> poison, i8 1, i64 0
+ %w = call <4 x i8> @llvm.bitreverse.v4i8(<4 x i8> %v0)
%e0 = extractelement <4 x i8> %w, i64 0
%cmp = icmp ne i8 %e0, 0
ret i1 %cmp
@@ -46,8 +46,8 @@ define i1 @rotl_lane0_nonzero() {
; CHECK-LABEL: rotl_lane0_nonzero:
; CHECK: mov{{.*}}1
; CHECK: ret
- %x = insertelement <4 x i8> undef, i8 2, i64 0 ; lane0 = 2 (non-zero)
- %k = insertelement <4 x i8> undef, i8 1, i64 0 ; rotate by 1
+ %x = insertelement <4 x i8> poison, i8 2, i64 0
+ %k = insertelement <4 x i8> poison, i8 1, i64 0
%w = call <4 x i8> @llvm.fshl.v4i8(<4 x i8> %x, <4 x i8> %x, <4 x i8> %k)
%e0 = extractelement <4 x i8> %w, i64 0
%cmp = icmp ne i8 %e0, 0
@@ -58,8 +58,8 @@ define i1 @rotr_lane0_nonzero() {
; CHECK-LABEL: rotr_lane0_nonzero:
; CHECK: mov{{.*}}1
; CHECK: ret
- %x = insertelement <4 x i8> undef, i8 2, i64 0
- %k = insertelement <4 x i8> undef, i8 1, i64 0
+ %x = insertelement <4 x i8> poison, i8 2, i64 0
+ %k = insertelement <4 x i8> poison, i8 1, i64 0
%w = call <4 x i8> @llvm.fshr.v4i8(<4 x i8> %x, <4 x i8> %x, <4 x i8> %k)
%e0 = extractelement <4 x i8> %w, i64 0
%cmp = icmp ne i8 %e0, 0
@@ -70,9 +70,9 @@ define i1 @abs_lane0_nonzero() {
; CHECK-LABEL: abs_lane0_nonzero:
; CHECK: mov{{.*}}1
; CHECK: ret
- %v0 = insertelement <4 x i8> undef, i8 -2, i64 0 ; lane0 = -2 (non-zero)
+ %v0 = insertelement <4 x i8> poison, i8 -2, i64 0
%w = call <4 x i8> @llvm.abs.v4i8(<4 x i8> %v0, i1 false)
%e0 = extractelement <4 x i8> %w, i64 0
%cmp = icmp ne i8 %e0, 0
ret i1 %cmp
-}
\ No newline at end of file
+}
>From 89e5b5f5efa40a30b7fee2fe1e002d4f19e83e6f Mon Sep 17 00:00:00 2001
From: Ayush3941 <ayushkgaur1 at gmail.com>
Date: Fri, 6 Mar 2026 10:42:10 -0500
Subject: [PATCH 3/4] [DAG] isKnownNeverZero: Add DemandedElts handling for
ROTL/ROTR/BITREVERSE/BSWAP/CTPOP/ABS update script tests
---
llvm/test/CodeGen/X86/known-never-zero.ll | 110 ++++++++++++++++++++++
1 file changed, 110 insertions(+)
diff --git a/llvm/test/CodeGen/X86/known-never-zero.ll b/llvm/test/CodeGen/X86/known-never-zero.ll
index 12bb486d8dceb..a058d54bade25 100644
--- a/llvm/test/CodeGen/X86/known-never-zero.ll
+++ b/llvm/test/CodeGen/X86/known-never-zero.ll
@@ -20,6 +20,12 @@ declare <4 x i32> @llvm.ctpop.v4i32(<4 x i32>)
declare i32 @llvm.abs.i32(i32, i1)
declare i32 @llvm.fshl.i32(i32, i32, i32)
declare i32 @llvm.fshr.i32(i32, i32, i32)
+declare <4 x i8> @llvm.ctpop.v4i8(<4 x i8>)
+declare <4 x i16> @llvm.bswap.v4i16(<4 x i16>)
+declare <4 x i8> @llvm.bitreverse.v4i8(<4 x i8>)
+declare <4 x i8> @llvm.fshl.v4i8(<4 x i8>, <4 x i8>, <4 x i8>)
+declare <4 x i8> @llvm.fshr.v4i8(<4 x i8>, <4 x i8>, <4 x i8>)
+declare <4 x i8> @llvm.abs.v4i8(<4 x i8>, i1)
define i32 @or_known_nonzero(i32 %x) {
; X86-LABEL: or_known_nonzero:
@@ -1465,3 +1471,107 @@ define i32 @sext_maybe_zero(i16 %x) {
%r = call i32 @llvm.cttz.i32(i32 %z, i1 false)
ret i32 %r
}
+
+define i1 @ctpop_lane0_nonzero() {
+; X86-LABEL: ctpop_lane0_nonzero:
+; X86: # %bb.0:
+; X86-NEXT: movb $1, %al
+; X86-NEXT: retl
+;
+; X64-LABEL: ctpop_lane0_nonzero:
+; X64: # %bb.0:
+; X64-NEXT: movb $1, %al
+; X64-NEXT: retq
+ %v0 = insertelement <4 x i8> poison, i8 8, i64 0
+ %w = call <4 x i8> @llvm.ctpop.v4i8(<4 x i8> %v0)
+ %e0 = extractelement <4 x i8> %w, i64 0
+ %cmp = icmp ne i8 %e0, 0
+ ret i1 %cmp
+}
+
+define i1 @bswap_lane0_nonzero() {
+; X86-LABEL: bswap_lane0_nonzero:
+; X86: # %bb.0:
+; X86-NEXT: movb $1, %al
+; X86-NEXT: retl
+;
+; X64-LABEL: bswap_lane0_nonzero:
+; X64: # %bb.0:
+; X64-NEXT: movb $1, %al
+; X64-NEXT: retq
+ %v0 = insertelement <4 x i16> poison, i16 1, i64 0
+ %w = call <4 x i16> @llvm.bswap.v4i16(<4 x i16> %v0)
+ %e0 = extractelement <4 x i16> %w, i64 0
+ %cmp = icmp ne i16 %e0, 0
+ ret i1 %cmp
+}
+
+define i1 @bitreverse_lane0_nonzero() {
+; X86-LABEL: bitreverse_lane0_nonzero:
+; X86: # %bb.0:
+; X86-NEXT: movb $1, %al
+; X86-NEXT: retl
+;
+; X64-LABEL: bitreverse_lane0_nonzero:
+; X64: # %bb.0:
+; X64-NEXT: movb $1, %al
+; X64-NEXT: retq
+ %v0 = insertelement <4 x i8> poison, i8 1, i64 0
+ %w = call <4 x i8> @llvm.bitreverse.v4i8(<4 x i8> %v0)
+ %e0 = extractelement <4 x i8> %w, i64 0
+ %cmp = icmp ne i8 %e0, 0
+ ret i1 %cmp
+}
+
+define i1 @rotl_lane0_nonzero() {
+; X86-LABEL: rotl_lane0_nonzero:
+; X86: # %bb.0:
+; X86-NEXT: movb $1, %al
+; X86-NEXT: retl
+;
+; X64-LABEL: rotl_lane0_nonzero:
+; X64: # %bb.0:
+; X64-NEXT: movb $1, %al
+; X64-NEXT: retq
+ %x = insertelement <4 x i8> poison, i8 2, i64 0
+ %k = insertelement <4 x i8> poison, i8 1, i64 0
+ %w = call <4 x i8> @llvm.fshl.v4i8(<4 x i8> %x, <4 x i8> %x, <4 x i8> %k)
+ %e0 = extractelement <4 x i8> %w, i64 0
+ %cmp = icmp ne i8 %e0, 0
+ ret i1 %cmp
+}
+
+define i1 @rotr_lane0_nonzero() {
+; X86-LABEL: rotr_lane0_nonzero:
+; X86: # %bb.0:
+; X86-NEXT: movb $1, %al
+; X86-NEXT: retl
+;
+; X64-LABEL: rotr_lane0_nonzero:
+; X64: # %bb.0:
+; X64-NEXT: movb $1, %al
+; X64-NEXT: retq
+ %x = insertelement <4 x i8> poison, i8 2, i64 0
+ %k = insertelement <4 x i8> poison, i8 1, i64 0
+ %w = call <4 x i8> @llvm.fshr.v4i8(<4 x i8> %x, <4 x i8> %x, <4 x i8> %k)
+ %e0 = extractelement <4 x i8> %w, i64 0
+ %cmp = icmp ne i8 %e0, 0
+ ret i1 %cmp
+}
+
+define i1 @abs_lane0_nonzero() {
+; X86-LABEL: abs_lane0_nonzero:
+; X86: # %bb.0:
+; X86-NEXT: movb $1, %al
+; X86-NEXT: retl
+;
+; X64-LABEL: abs_lane0_nonzero:
+; X64: # %bb.0:
+; X64-NEXT: movb $1, %al
+; X64-NEXT: retq
+ %v0 = insertelement <4 x i8> poison, i8 -2, i64 0
+ %w = call <4 x i8> @llvm.abs.v4i8(<4 x i8> %v0, i1 false)
+ %e0 = extractelement <4 x i8> %w, i64 0
+ %cmp = icmp ne i8 %e0, 0
+ ret i1 %cmp
+}
>From 215756cb95f1a8993de67e2e370237800bef7d8e Mon Sep 17 00:00:00 2001
From: Ayush3941 <ayushkgaur1 at gmail.com>
Date: Fri, 6 Mar 2026 11:43:43 -0500
Subject: [PATCH 4/4] [DAG] isKnownNeverZero: Add DemandedElts handling for
ROTL/ROTR/BITREVERSE/BSWAP/CTPOP/ABS v3
---
.../X86/known-never-zero-demanded-elts.ll | 78 -------------------
1 file changed, 78 deletions(-)
delete mode 100644 llvm/test/CodeGen/X86/known-never-zero-demanded-elts.ll
diff --git a/llvm/test/CodeGen/X86/known-never-zero-demanded-elts.ll b/llvm/test/CodeGen/X86/known-never-zero-demanded-elts.ll
deleted file mode 100644
index 34942bf8d9ab5..0000000000000
--- a/llvm/test/CodeGen/X86/known-never-zero-demanded-elts.ll
+++ /dev/null
@@ -1,78 +0,0 @@
-; RUN: llc -O2 -mtriple=x86_64-unknown-linux-gnu %s -o - | FileCheck %s
-
-; Helper: build vector with lane0 set, other lanes poison.
-
-declare <4 x i8> @llvm.ctpop.v4i8(<4 x i8>)
-declare <4 x i16> @llvm.bswap.v4i16(<4 x i16>)
-declare <4 x i8> @llvm.bitreverse.v4i8(<4 x i8>)
-declare <4 x i8> @llvm.fshl.v4i8(<4 x i8>, <4 x i8>, <4 x i8>)
-declare <4 x i8> @llvm.fshr.v4i8(<4 x i8>, <4 x i8>, <4 x i8>)
-declare <4 x i8> @llvm.abs.v4i8(<4 x i8>, i1)
-
-define i1 @ctpop_lane0_nonzero() {
-; CHECK-LABEL: ctpop_lane0_nonzero:
-; CHECK: mov{{.*}}1
-; CHECK: ret
- %v0 = insertelement <4 x i8> poison, i8 8, i64 0
- %w = call <4 x i8> @llvm.ctpop.v4i8(<4 x i8> %v0)
- %e0 = extractelement <4 x i8> %w, i64 0
- %cmp = icmp ne i8 %e0, 0
- ret i1 %cmp
-}
-
-define i1 @bswap_lane0_nonzero() {
-; CHECK-LABEL: bswap_lane0_nonzero:
-; CHECK: mov{{.*}}1
-; CHECK: ret
- %v0 = insertelement <4 x i16> poison, i16 1, i64 0
- %w = call <4 x i16> @llvm.bswap.v4i16(<4 x i16> %v0)
- %e0 = extractelement <4 x i16> %w, i64 0
- %cmp = icmp ne i16 %e0, 0
- ret i1 %cmp
-}
-
-define i1 @bitreverse_lane0_nonzero() {
-; CHECK-LABEL: bitreverse_lane0_nonzero:
-; CHECK: mov{{.*}}1
-; CHECK: ret
- %v0 = insertelement <4 x i8> poison, i8 1, i64 0
- %w = call <4 x i8> @llvm.bitreverse.v4i8(<4 x i8> %v0)
- %e0 = extractelement <4 x i8> %w, i64 0
- %cmp = icmp ne i8 %e0, 0
- ret i1 %cmp
-}
-
-define i1 @rotl_lane0_nonzero() {
-; CHECK-LABEL: rotl_lane0_nonzero:
-; CHECK: mov{{.*}}1
-; CHECK: ret
- %x = insertelement <4 x i8> poison, i8 2, i64 0
- %k = insertelement <4 x i8> poison, i8 1, i64 0
- %w = call <4 x i8> @llvm.fshl.v4i8(<4 x i8> %x, <4 x i8> %x, <4 x i8> %k)
- %e0 = extractelement <4 x i8> %w, i64 0
- %cmp = icmp ne i8 %e0, 0
- ret i1 %cmp
-}
-
-define i1 @rotr_lane0_nonzero() {
-; CHECK-LABEL: rotr_lane0_nonzero:
-; CHECK: mov{{.*}}1
-; CHECK: ret
- %x = insertelement <4 x i8> poison, i8 2, i64 0
- %k = insertelement <4 x i8> poison, i8 1, i64 0
- %w = call <4 x i8> @llvm.fshr.v4i8(<4 x i8> %x, <4 x i8> %x, <4 x i8> %k)
- %e0 = extractelement <4 x i8> %w, i64 0
- %cmp = icmp ne i8 %e0, 0
- ret i1 %cmp
-}
-
-define i1 @abs_lane0_nonzero() {
-; CHECK-LABEL: abs_lane0_nonzero:
-; CHECK: mov{{.*}}1
-; CHECK: ret
- %v0 = insertelement <4 x i8> poison, i8 -2, i64 0
- %w = call <4 x i8> @llvm.abs.v4i8(<4 x i8> %v0, i1 false)
- %e0 = extractelement <4 x i8> %w, i64 0
- %cmp = icmp ne i8 %e0, 0
- ret i1 %cmp
-}
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