[llvm] Simplify demanded (PR #185113)

[via llvm-commits]

https://github.com/SiliconA-Z created https://github.com/llvm/llvm-project/pull/185113

None

>From 51e40f34d07bac5cb6510ef8ea32a81dd4f932dd Mon Sep 17 00:00:00 2001
From: AZero13 <gfunni234 at gmail.com>
Date: Fri, 6 Mar 2026 16:21:36 -0500
Subject: [PATCH] Simplify demanded

---
 llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp | 14 ++++++++++++--
 1 file changed, 12 insertions(+), 2 deletions(-)

diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 088e6726fea58..40cf9891a83e1 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -1506,11 +1506,21 @@ bool TargetLowering::SimplifyDemandedBits(
       }
     }
 
+    // Compute the known bits of Op1 without forcing a deep recursive simplify
+    // so that we can appropriately narrow the DemandedBits for Op0.
+    KnownBits Op1Known = TLO.DAG.computeKnownBits(Op1, DemandedElts, Depth + 1);
+
     if (SimplifyDemandedBits(Op1, DemandedBits, DemandedElts, Known, TLO,
                              Depth + 1))
       return true;
-    if (SimplifyDemandedBits(Op0, ~Known.Zero & DemandedBits, DemandedElts,
-                             Known2, TLO, Depth + 1))
+    if (SimplifyDemandedBits(Op0, ~Op1Known.Zero & ~Known.Zero & DemandedBits,
+                             DemandedElts, Known2, TLO, Depth + 1))
+      return true;
+    // If we still haven't simplified the node, it may be because Op1 could be
+    // simplified using Op0's known zeros.
+    if ((~Known2.Zero & DemandedBits) != DemandedBits &&
+        SimplifyDemandedBits(Op1, ~Known2.Zero & DemandedBits, DemandedElts,
+                             Known, TLO, Depth + 1))
       return true;
 
     // If all of the demanded bits are known one on one side, return the other.