[llvm] bb1d53b - [RISCV][P-ext] Support vector ISD::ABS using PABD instructions. (#184822)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Mar 6 10:21:30 PST 2026
Author: Craig Topper
Date: 2026-03-06T10:21:25-08:00
New Revision: bb1d53bbd8726160ed2e45bb4170454b4d8d2d9b
URL: https://github.com/llvm/llvm-project/commit/bb1d53bbd8726160ed2e45bb4170454b4d8d2d9b
DIFF: https://github.com/llvm/llvm-project/commit/bb1d53bbd8726160ed2e45bb4170454b4d8d2d9b.diff
LOG: [RISCV][P-ext] Support vector ISD::ABS using PABD instructions. (#184822)
Added:
Modified:
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/lib/Target/RISCV/RISCVInstrInfoP.td
llvm/test/CodeGen/RISCV/rvp-ext-rv32.ll
llvm/test/CodeGen/RISCV/rvp-ext-rv64.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 891bc22a7463d..17d7db95886ab 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -576,7 +576,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
setOperationAction({ISD::AVGFLOORS, ISD::AVGFLOORU}, VTs, Legal);
for (MVT VT : VTs) {
if (VT != MVT::v2i32)
- setOperationAction({ISD::ABDS, ISD::ABDU}, VT, Legal);
+ setOperationAction({ISD::ABS, ISD::ABDS, ISD::ABDU}, VT, Legal);
if (VT.getVectorElementType() != MVT::i8)
setOperationAction(ISD::SSHLSAT, VT, Legal);
}
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoP.td b/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
index 7bb9ad5feb219..c0e392ca04b0a 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
@@ -1755,10 +1755,12 @@ let Predicates = [HasStdExtP] in {
def: Pat<(XLenVecI16VT (riscv_asubu GPR:$rs1, GPR:$rs2)), (PASUBU_H GPR:$rs1, GPR:$rs2)>;
// 8-bit absolute
diff erence patterns
+ def: Pat<(XLenVecI8VT (abs GPR:$rs1)), (PABD_B GPR:$rs1, (XLenVecI8VT X0))>;
def: Pat<(XLenVecI8VT (abds GPR:$rs1, GPR:$rs2)), (PABD_B GPR:$rs1, GPR:$rs2)>;
def: Pat<(XLenVecI8VT (abdu GPR:$rs1, GPR:$rs2)), (PABDU_B GPR:$rs1, GPR:$rs2)>;
// 16-bit absolute
diff erence patterns
+ def: Pat<(XLenVecI16VT (abs GPR:$rs1)), (PABD_H GPR:$rs1, (XLenVecI16VT X0))>;
def: Pat<(XLenVecI16VT (abds GPR:$rs1, GPR:$rs2)), (PABD_H GPR:$rs1, GPR:$rs2)>;
def: Pat<(XLenVecI16VT (abdu GPR:$rs1, GPR:$rs2)), (PABDU_H GPR:$rs1, GPR:$rs2)>;
diff --git a/llvm/test/CodeGen/RISCV/rvp-ext-rv32.ll b/llvm/test/CodeGen/RISCV/rvp-ext-rv32.ll
index 581f962538797..49b06b5ca5593 100644
--- a/llvm/test/CodeGen/RISCV/rvp-ext-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvp-ext-rv32.ll
@@ -310,6 +310,24 @@ define <4 x i8> @test_paaddu_b(<4 x i8> %a, <4 x i8> %b) {
ret <4 x i8> %res
}
+define <2 x i16> @test_pabs_h(<2 x i16> %a) {
+; CHECK-LABEL: test_pabs_h:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pabd.h a0, a0, zero
+; CHECK-NEXT: ret
+ %res = call <2 x i16> @llvm.abs.v2i16(<2 x i16> %a, i1 0)
+ ret <2 x i16> %res
+}
+
+define <4 x i8> @test_pabs_b(<4 x i8> %a) {
+; CHECK-LABEL: test_pabs_b:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pabd.b a0, a0, zero
+; CHECK-NEXT: ret
+ %res = call <4 x i8> @llvm.abs.v4i8(<4 x i8> %a, i1 0)
+ ret <4 x i8> %res
+}
+
; Test absolute
diff erence signed for v2i16
define <2 x i16> @test_pdif_h(<2 x i16> %a, <2 x i16> %b) {
; CHECK-LABEL: test_pdif_h:
@@ -1744,10 +1762,10 @@ define <2 x i16> @test_select_v2i16(i1 %cond, <2 x i16> %a, <2 x i16> %b) {
; CHECK: # %bb.0:
; CHECK-NEXT: andi a3, a0, 1
; CHECK-NEXT: mv a0, a1
-; CHECK-NEXT: bnez a3, .LBB124_2
+; CHECK-NEXT: bnez a3, .LBB126_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a0, a2
-; CHECK-NEXT: .LBB124_2:
+; CHECK-NEXT: .LBB126_2:
; CHECK-NEXT: ret
%res = select i1 %cond, <2 x i16> %a, <2 x i16> %b
ret <2 x i16> %res
@@ -1758,10 +1776,10 @@ define <4 x i8> @test_select_v4i8(i1 %cond, <4 x i8> %a, <4 x i8> %b) {
; CHECK: # %bb.0:
; CHECK-NEXT: andi a3, a0, 1
; CHECK-NEXT: mv a0, a1
-; CHECK-NEXT: bnez a3, .LBB125_2
+; CHECK-NEXT: bnez a3, .LBB127_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a0, a2
-; CHECK-NEXT: .LBB125_2:
+; CHECK-NEXT: .LBB127_2:
; CHECK-NEXT: ret
%res = select i1 %cond, <4 x i8> %a, <4 x i8> %b
ret <4 x i8> %res
diff --git a/llvm/test/CodeGen/RISCV/rvp-ext-rv64.ll b/llvm/test/CodeGen/RISCV/rvp-ext-rv64.ll
index 36bb90c8f099c..e7a11506da22b 100644
--- a/llvm/test/CodeGen/RISCV/rvp-ext-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvp-ext-rv64.ll
@@ -374,6 +374,34 @@ define <8 x i8> @test_paaddu_b(<8 x i8> %a, <8 x i8> %b) {
ret <8 x i8> %res
}
+define <2 x i32> @test_pabs_w(<2 x i32> %a) {
+; CHECK-LABEL: test_pabs_w:
+; CHECK: # %bb.0:
+; CHECK-NEXT: psub.w a1, zero, a0
+; CHECK-NEXT: pmax.w a0, a0, a1
+; CHECK-NEXT: ret
+ %res = call <2 x i32> @llvm.abs.v2i32(<2 x i32> %a, i1 0)
+ ret <2 x i32> %res
+}
+
+define <4 x i16> @test_pabs_h(<4 x i16> %a) {
+; CHECK-LABEL: test_pabs_h:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pabd.h a0, a0, zero
+; CHECK-NEXT: ret
+ %res = call <4 x i16> @llvm.abs.v4i16(<4 x i16> %a, i1 0)
+ ret <4 x i16> %res
+}
+
+define <8 x i8> @test_pabs_b(<8 x i8> %a) {
+; CHECK-LABEL: test_pabs_b:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pabd.b a0, a0, zero
+; CHECK-NEXT: ret
+ %res = call <8 x i8> @llvm.abs.v8i8(<8 x i8> %a, i1 0)
+ ret <8 x i8> %res
+}
+
; Test absolute
diff erence signed for v2i32
; abds pattern: sub(smax(a,b), smin(a,b))
define <2 x i32> @test_pdif_w(<2 x i32> %a, <2 x i32> %b) {
@@ -2130,10 +2158,10 @@ define <4 x i16> @test_select_v4i16(i1 %cond, <4 x i16> %a, <4 x i16> %b) {
; CHECK: # %bb.0:
; CHECK-NEXT: andi a3, a0, 1
; CHECK-NEXT: mv a0, a1
-; CHECK-NEXT: bnez a3, .LBB174_2
+; CHECK-NEXT: bnez a3, .LBB177_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a0, a2
-; CHECK-NEXT: .LBB174_2:
+; CHECK-NEXT: .LBB177_2:
; CHECK-NEXT: ret
%res = select i1 %cond, <4 x i16> %a, <4 x i16> %b
ret <4 x i16> %res
@@ -2144,10 +2172,10 @@ define <8 x i8> @test_select_v8i8(i1 %cond, <8 x i8> %a, <8 x i8> %b) {
; CHECK: # %bb.0:
; CHECK-NEXT: andi a3, a0, 1
; CHECK-NEXT: mv a0, a1
-; CHECK-NEXT: bnez a3, .LBB175_2
+; CHECK-NEXT: bnez a3, .LBB178_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a0, a2
-; CHECK-NEXT: .LBB175_2:
+; CHECK-NEXT: .LBB178_2:
; CHECK-NEXT: ret
%res = select i1 %cond, <8 x i8> %a, <8 x i8> %b
ret <8 x i8> %res
@@ -2158,10 +2186,10 @@ define <2 x i32> @test_select_v2i32(i1 %cond, <2 x i32> %a, <2 x i32> %b) {
; CHECK: # %bb.0:
; CHECK-NEXT: andi a3, a0, 1
; CHECK-NEXT: mv a0, a1
-; CHECK-NEXT: bnez a3, .LBB176_2
+; CHECK-NEXT: bnez a3, .LBB179_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a0, a2
-; CHECK-NEXT: .LBB176_2:
+; CHECK-NEXT: .LBB179_2:
; CHECK-NEXT: ret
%res = select i1 %cond, <2 x i32> %a, <2 x i32> %b
ret <2 x i32> %res
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