[llvm] [AArch64] Fix more typos (NFC) (PR #183086)
Jonathan Thackray via llvm-commits
llvm-commits at lists.llvm.org
Fri Mar 6 09:55:26 PST 2026
https://github.com/jthackray updated https://github.com/llvm/llvm-project/pull/183086
>From ef17b481796920133107871d60eef9beffbb5166 Mon Sep 17 00:00:00 2001
From: Jonathan Thackray <jonathan.thackray at arm.com>
Date: Tue, 24 Feb 2026 16:03:20 +0000
Subject: [PATCH 1/2] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?=
=?UTF-8?q?itial=20version?=
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Created using spr 1.3.7
---
llvm/lib/Target/AArch64/AArch64Arm64ECCallLowering.cpp | 2 +-
llvm/lib/Target/AArch64/AArch64CollectLOH.cpp | 2 +-
llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp | 2 +-
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp | 4 ++--
llvm/lib/Target/AArch64/AArch64MCInstLower.cpp | 2 +-
llvm/lib/Target/AArch64/AArch64PromoteConstant.cpp | 2 +-
llvm/lib/Target/AArch64/AArch64SRLTDefineSuperRegs.cpp | 2 +-
llvm/lib/Target/AArch64/AArch64StackTagging.cpp | 2 +-
llvm/lib/Target/AArch64/AArch64TargetMachine.cpp | 2 +-
llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp | 2 +-
llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp | 2 +-
llvm/lib/Target/AArch64/MachineSMEABIPass.cpp | 4 ++--
12 files changed, 14 insertions(+), 14 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64Arm64ECCallLowering.cpp b/llvm/lib/Target/AArch64/AArch64Arm64ECCallLowering.cpp
index c27a693ceecc1..c09e88c083c1f 100644
--- a/llvm/lib/Target/AArch64/AArch64Arm64ECCallLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64Arm64ECCallLowering.cpp
@@ -251,7 +251,7 @@ void AArch64Arm64ECCallLowering::getThunkRetType(
// actually equivalent to just passing and returning a void* pointer
// as the first or second argument. Translate it that way, instead of
// trying to model "inreg" in the thunk's calling convention; this
- // simplfies the rest of the code, and matches MSVC mangling.
+ // simplifies the rest of the code, and matches MSVC mangling.
Out << "i8";
Arm64RetTy = I64Ty;
X64RetTy = I64Ty;
diff --git a/llvm/lib/Target/AArch64/AArch64CollectLOH.cpp b/llvm/lib/Target/AArch64/AArch64CollectLOH.cpp
index 064716216d1cb..069147a1b669b 100644
--- a/llvm/lib/Target/AArch64/AArch64CollectLOH.cpp
+++ b/llvm/lib/Target/AArch64/AArch64CollectLOH.cpp
@@ -80,7 +80,7 @@
// - .loh AdrpAdrp L2, L1:
// L2: ADRP xA, sym1 at PAGE
// L1: ADRP xA, sym2 at PAGE
-// L2 dominates L1 and xA is not redifined between L2 and L1
+// L2 dominates L1 and xA is not redefined between L2 and L1
// This LOH aims at getting rid of redundant ADRP instructions.
//
// The overall design for emitting the LOHs is:
diff --git a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
index 67f4e127b0c87..4c3d477033bf9 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
@@ -4625,7 +4625,7 @@ bool AArch64DAGToDAGISel::trySelectXAR(SDNode *N) {
SDLoc DL(N);
// Essentially: rotr (xor(x, y), imm) -> xar (x, y, imm)
- // Rotate by a constant is a funnel shift in IR which is exanded to
+ // Rotate by a constant is a funnel shift in IR which is expanded to
// an OR with shifted operands.
// We do the following transform:
// OR N0, N1 -> xar (x, y, imm)
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 7af6db793892b..bb94c4258b51c 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -4054,7 +4054,7 @@ static bool canEmitConjunction(SelectionDAG &DAG, const SDValue Val,
if (!CanNegateL && !CanNegateR)
return false;
// If we the result of the OR will be negated and we can naturally negate
- // the leafs, then this sub-tree as a whole negates naturally.
+ // the leaves, then this sub-tree as a whole negates naturally.
CanNegate = WillNegate && CanNegateL && CanNegateR;
// If we cannot naturally negate the whole sub-tree, then this must be
// emitted first.
@@ -24066,7 +24066,7 @@ static SDValue performZExtDeinterleaveShuffleCombine(SDNode *N,
unsigned Idx;
bool IsDeInterleave = ShuffleVectorInst::isDeInterleaveMaskOfFactor(
Shuffle->getMask().slice(ExtOffset, VT.getVectorNumElements()), 4, Idx);
- // An undef interleave shuffle can come up after other canonicalizations,
+ // An undef interleave shuffle can come up after other canonicalization,
// where the shuffle has been converted to
// zext(extract(shuffle b, undef, [u,u,0,4]))
bool IsUndefDeInterleave = false;
diff --git a/llvm/lib/Target/AArch64/AArch64MCInstLower.cpp b/llvm/lib/Target/AArch64/AArch64MCInstLower.cpp
index 39946633603f6..d3a38624488e8 100644
--- a/llvm/lib/Target/AArch64/AArch64MCInstLower.cpp
+++ b/llvm/lib/Target/AArch64/AArch64MCInstLower.cpp
@@ -102,7 +102,7 @@ MCSymbol *AArch64MCInstLower::GetGlobalValueSymbol(const GlobalValue *GV,
//
// If we see a reference to an "aux" symbol, also emit a reference to the
// corresponding non-aux symbol. Otherwise, the Microsoft linker behaves
- // strangely when linking against x64 import libararies.
+ // strangely when linking against x64 import libraries.
//
// emitSymbolAttribute() doesn't have any real effect here; it just
// ensures the symbol name appears in the assembly without any
diff --git a/llvm/lib/Target/AArch64/AArch64PromoteConstant.cpp b/llvm/lib/Target/AArch64/AArch64PromoteConstant.cpp
index 1a9ce869f5dfa..01cf9c3e7eb56 100644
--- a/llvm/lib/Target/AArch64/AArch64PromoteConstant.cpp
+++ b/llvm/lib/Target/AArch64/AArch64PromoteConstant.cpp
@@ -246,7 +246,7 @@ static bool isConstantUsingVectorTy(const Type *CstTy) {
return false;
}
-// Returns true if \p C contains only ConstantData leafs and no global values,
+// Returns true if \p C contains only ConstantData leaves and no global values,
// block addresses or constant expressions. Traverses ConstantAggregates.
static bool containsOnlyConstantData(const Constant *C) {
if (isa<ConstantData>(C))
diff --git a/llvm/lib/Target/AArch64/AArch64SRLTDefineSuperRegs.cpp b/llvm/lib/Target/AArch64/AArch64SRLTDefineSuperRegs.cpp
index 40345769a64d9..cb881692c43f0 100644
--- a/llvm/lib/Target/AArch64/AArch64SRLTDefineSuperRegs.cpp
+++ b/llvm/lib/Target/AArch64/AArch64SRLTDefineSuperRegs.cpp
@@ -32,7 +32,7 @@
// that we can enable SRLT for AArch64.
//
// The approach here is to just add the 'implicit-def' manually after rewriting
-// virtual regs -> phsyical regs. This still means that during the register
+// virtual regs -> physical regs. This still means that during the register
// allocation process the dependences are not accurately represented in the MIR
// and LiveIntervals, but there are several reasons why we believe this isn't a
// problem in practice:
diff --git a/llvm/lib/Target/AArch64/AArch64StackTagging.cpp b/llvm/lib/Target/AArch64/AArch64StackTagging.cpp
index 3e099e8216266..5e07956f20674 100644
--- a/llvm/lib/Target/AArch64/AArch64StackTagging.cpp
+++ b/llvm/lib/Target/AArch64/AArch64StackTagging.cpp
@@ -220,7 +220,7 @@ class InitializerBuilder {
}
// Look through 8-byte initializer list 16 bytes at a time;
- // If one of the two 8-byte halfs is non-zero non-undef, emit STGP.
+ // If one of the two 8-byte halves is non-zero non-undef, emit STGP.
// Otherwise, emit zeroes up to next available item.
uint64_t LastOffset = 0;
for (uint64_t Offset = 0; Offset < Size; Offset += 16) {
diff --git a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
index 652844e9dc591..7def8356c6f08 100644
--- a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
+++ b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
@@ -612,7 +612,7 @@ std::unique_ptr<CSEConfigBase> AArch64PassConfig::getCSEConfig() const {
return getStandardCSEConfigForOpt(TM->getOptLevel());
}
-// This function checks whether the opt level is explictly set to none,
+// This function checks whether the opt level is explicitly set to none,
// or whether GlobalISel was enabled due to SDAG encountering an optnone
// function. If the opt level is greater than the level we automatically enable
// globalisel at, and it wasn't enabled via CLI, we know that it must be because
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
index 32c91831d9fb7..9bf1c323e5c15 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
@@ -4547,7 +4547,7 @@ MachineInstr *AArch64InstructionSelector::emitFPCompare(
P == CmpInst::FCMP_UEQ || P == CmpInst::FCMP_UNE;
};
if (!ShouldUseImm && Pred && IsEqualityPred(*Pred)) {
- // Try commutating the operands.
+ // Try commuting the operands.
const ConstantFP *LHSImm = getConstantFPVRegVal(LHS, MRI);
if (LHSImm && (LHSImm->isZero() && !LHSImm->isNegative())) {
ShouldUseImm = true;
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp b/llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp
index 45cbe7b5aa2fe..43e74405ac965 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp
@@ -462,7 +462,7 @@ void applyExtUaddvToUaddlv(MachineInstr &MI, MachineRegisterInfo &MRI,
LLT DstTy = MRI.getType(DstReg);
// If SrcTy has more elements than expected, split them into multiple
- // insructions and sum the results
+ // instructions and sum the results
LLT MainTy;
SmallVector<Register, 1> WorkingRegisters;
unsigned SrcScalSize = SrcTy.getScalarSizeInBits();
diff --git a/llvm/lib/Target/AArch64/MachineSMEABIPass.cpp b/llvm/lib/Target/AArch64/MachineSMEABIPass.cpp
index 07abaf92d23d5..aec764d5bc7a0 100644
--- a/llvm/lib/Target/AArch64/MachineSMEABIPass.cpp
+++ b/llvm/lib/Target/AArch64/MachineSMEABIPass.cpp
@@ -1129,7 +1129,7 @@ void MachineSMEABI::emitStateChange(EmitContext &Context,
// This section handles: LOCAL_COMMITTED -> (OFF|LOCAL_SAVED)
case transitionFrom(ZAState::LOCAL_COMMITTED).to(ZAState::OFF):
case transitionFrom(ZAState::LOCAL_COMMITTED).to(ZAState::LOCAL_SAVED):
- // These transistions are a no-op.
+ // These transitions are a no-op.
break;
// This section handles: LOCAL_(SAVED|COMMITTED) -> ACTIVE[_ZT0_SAVED]
@@ -1145,7 +1145,7 @@ void MachineSMEABI::emitStateChange(EmitContext &Context,
emitZT0SaveRestore(Context, MBB, InsertPt, /*IsSave=*/false);
break;
- // This section handles transistions to OFF (not previously covered)
+ // This section handles transitions to OFF (not previously covered)
case transitionFrom(ZAState::ACTIVE).to(ZAState::OFF):
case transitionFrom(ZAState::ACTIVE_ZT0_SAVED).to(ZAState::OFF):
case transitionFrom(ZAState::LOCAL_SAVED).to(ZAState::OFF):
>From 5a6e027ff8197286fc9047dfba29c50de0155da1 Mon Sep 17 00:00:00 2001
From: Jonathan Thackray <jonathan.thackray at arm.com>
Date: Thu, 5 Mar 2026 23:35:37 +0000
Subject: [PATCH 2/2] fix Dave Green's comment
Created using spr 1.3.7
---
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index bb94c4258b51c..f68e732d362de 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -24066,7 +24066,7 @@ static SDValue performZExtDeinterleaveShuffleCombine(SDNode *N,
unsigned Idx;
bool IsDeInterleave = ShuffleVectorInst::isDeInterleaveMaskOfFactor(
Shuffle->getMask().slice(ExtOffset, VT.getVectorNumElements()), 4, Idx);
- // An undef interleave shuffle can come up after other canonicalization,
+ // An undef interleave shuffle can come up after other canonicalizations,
// where the shuffle has been converted to
// zext(extract(shuffle b, undef, [u,u,0,4]))
bool IsUndefDeInterleave = false;
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