[lldb] [llvm] [AArch64][llvm] Tighten SYSP parsing; don't disassemble invalid encodings (PR #182410)

[Jonathan Thackray via llvm-commits]

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@@ -13,150 +13,150 @@
 // registers with 128-bit formats (op0, op1, Cn, Cm, op2)
 // For sysp, op0 is 0
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jthackray wrote:

Agreed, I've added some more tests here, but there may be more scope for additional testing.

https://github.com/llvm/llvm-project/pull/182410