[clang] [llvm] Add AMO load with Compare and Swap Not Equal (PR #178061)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Mar 6 08:20:41 PST 2026
================
@@ -11506,6 +11480,48 @@ SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
return Flags;
}
+SDValue PPCTargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op,
+ SelectionDAG &DAG) const {
+ unsigned IntrinsicID = Op.getConstantOperandVal(1);
+ SDLoc dl(Op);
+ switch (IntrinsicID) {
+ case Intrinsic::ppc_amo_lwat_csne:
+ case Intrinsic::ppc_amo_ldat_csne:
+ SDValue Chain = Op.getOperand(0);
+ SDValue Ptr = Op.getOperand(2);
+ SDValue CmpVal = Op.getOperand(3);
+ SDValue NewVal = Op.getOperand(4);
+
+ EVT VT = IntrinsicID == Intrinsic::ppc_amo_ldat_csne ? MVT::i64 : MVT::i32;
+ Type *Ty = VT.getTypeForEVT(*DAG.getContext());
+ Type *IntPtrTy = DAG.getDataLayout().getIntPtrType(*DAG.getContext());
+
+ TargetLowering::ArgListTy Args;
+ Args.emplace_back(DAG.getUNDEF(VT), Ty);
+ Args.emplace_back(CmpVal, Ty);
+ Args.emplace_back(NewVal, Ty);
+ Args.emplace_back(Ptr, IntPtrTy);
+
+ // Lower to dummy call to use ABI for consecutive register allocation.
+ // Places return value, compare value, and new value in X3/X4/X5 as required
+ // by lwat/ldat FC=16, avoiding a new register class for 3 adjacent
+ // registers.
+ const char *SymName = IntrinsicID == Intrinsic::ppc_amo_ldat_csne
+ ? "__ldat_csne_dummy"
+ : "__lwat_csne_dummy";
----------------
RolandF77 wrote:
I think we should avoid terms like dummy in instructions that appear in traces. Maybe use pseudo or macro or something.
https://github.com/llvm/llvm-project/pull/178061
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