[llvm] [SPIRV][Debug Info] DebugCompilationUnit refactor for DebugFunction support (PR #183117)

[Manuel Carrasco via llvm-commits]

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@@ -64,58 +94,92 @@ enum BaseTypeAttributeEncoding {
   UnsignedChar = 7
 };
 
-enum SourceLanguage {
-  Unknown = 0,
-  ESSL = 1,
-  GLSL = 2,
-  OpenCL_C = 3,
-  OpenCL_CPP = 4,
-  HLSL = 5,
-  CPP_for_OpenCL = 6,
-  SYCL = 7,
-  HERO_C = 8,
-  NZSL = 9,
-  WGSL = 10,
-  Slang = 11,
-  Zig = 12
-};
+SourceLanguage SPIRVEmitNonSemanticDI::convertDWARFToSPIRVSourceLanguage(
+    int64_t LLVMSourceLanguage) {
+  switch (LLVMSourceLanguage) {
+  case dwarf::DW_LANG_OpenCL:
+    return SourceLanguage::OpenCL_C;
+  case dwarf::DW_LANG_OpenCL_CPP:
+    return SourceLanguage::OpenCL_CPP;
+  case dwarf::DW_LANG_CPP_for_OpenCL:
+    return SourceLanguage::CPP_for_OpenCL;
+  case dwarf::DW_LANG_GLSL:
+    return SourceLanguage::GLSL;
+  case dwarf::DW_LANG_HLSL:
+    return SourceLanguage::HLSL;
+  case dwarf::DW_LANG_SYCL:
+    return SourceLanguage::SYCL;
+  case dwarf::DW_LANG_Zig:
+    return SourceLanguage::Zig;
+  default:
+    return SourceLanguage::Unknown;
+  }
+}
+
+static const Module *getModule(MachineFunction &MF) {
+  return MF.getFunction().getParent();
+}
+
+Register SPIRVEmitNonSemanticDI::emitOpString(MachineRegisterInfo &MRI,
+                                              MachineIRBuilder &MIRBuilder,
+                                              StringRef SR) {
+  const Register StrReg = MRI.createVirtualRegister(&SPIRV::IDRegClass);
+  MRI.setType(StrReg, LLT::scalar(32));
+  MachineInstrBuilder MIB = MIRBuilder.buildInstr(SPIRV::OpString);
+  MIB.addDef(StrReg);
+  addStringImm(SR, MIB);
+  return StrReg;
+}
+
+Register SPIRVEmitNonSemanticDI::emitDIInstruction(
+    MachineRegisterInfo &MRI, MachineIRBuilder &MIRBuilder,
+    SPIRVGlobalRegistry *GR, const SPIRVTypeInst &VoidTy,
+    const SPIRVInstrInfo *TII, const SPIRVRegisterInfo *TRI,
+    const RegisterBankInfo *RBI, MachineFunction &MF,
+    SPIRV::NonSemanticExtInst::NonSemanticExtInst Inst,
+    ArrayRef<Register> Registers) {
+  const Register InstReg = MRI.createVirtualRegister(&SPIRV::IDRegClass);
+  MRI.setType(InstReg, LLT::scalar(32));
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mgcarrasco wrote:

Ty. Switched to scalar(64) for consistency.

https://github.com/llvm/llvm-project/pull/183117