[llvm] [AArch64][SVE2] Allow commuting two-input NBSL/BSL2N idioms. (PR #184847)

[Ricardo Jesus via llvm-commits]

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@@ -4147,6 +4147,22 @@ let Predicates = [HasSVE2_or_SME] in {
   defm BSL2N_ZZZZ : sve2_int_bitwise_ternary_op<0b101, "bsl2n", AArch64bsl2n>;
   defm NBSL_ZZZZ  : sve2_int_bitwise_ternary_op<0b111, "nbsl",  AArch64nbsl>;
 
+  // Pseudos for commutable operations that expand to NBSL or BSL2N. These can
+  // avoid a COPY if one of the source registers can be clobbered.
+  let isCommutable = 1, hasSideEffects = 0 in {
+    // EON (a, b) = BSL2N (a, a, b) = BSL2N (b, b, a)
+    def EON_ZZZ : Pseudo<(outs ZPR64:$Zdn), (ins ZPR64:$_Zdn, ZPR64:$Zm), [], "$Zdn = $_Zdn">,
+                  PseudoInstExpansion<(BSL2N_ZZZZ ZPR64:$Zdn, ZPR64:$_Zdn, ZPR64:$_Zdn, ZPR64:$Zm)>;
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rj-jesus wrote:

Thanks, I'll update the PR to go that route then. However, how would we expand any arbitrary ternary bit selection pattern? We can do so for the binary patterns in this PR because we know the inputs can be commuted if one matches the allocated destination register, and if not, we can emit a movprfx for the copy. But how would we expand something like `BSLN_ZZZZ z0, z1, z2, z0`, for example?

https://github.com/llvm/llvm-project/pull/184847