[llvm] [AArch64][SVE2] Allow commuting two-input NBSL/BSL2N idioms. (PR #184847)

[Paul Walker via llvm-commits]

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@@ -4147,6 +4147,22 @@ let Predicates = [HasSVE2_or_SME] in {
   defm BSL2N_ZZZZ : sve2_int_bitwise_ternary_op<0b101, "bsl2n", AArch64bsl2n>;
   defm NBSL_ZZZZ  : sve2_int_bitwise_ternary_op<0b111, "nbsl",  AArch64nbsl>;
 
+  // Pseudos for commutable operations that expand to NBSL or BSL2N. These can
+  // avoid a COPY if one of the source registers can be clobbered.
+  let isCommutable = 1, hasSideEffects = 0 in {
+    // EON (a, b) = BSL2N (a, a, b) = BSL2N (b, b, a)
+    def EON_ZZZ : Pseudo<(outs ZPR64:$Zdn), (ins ZPR64:$_Zdn, ZPR64:$Zm), [], "$Zdn = $_Zdn">,
+                  PseudoInstExpansion<(BSL2N_ZZZZ ZPR64:$Zdn, ZPR64:$_Zdn, ZPR64:$_Zdn, ZPR64:$Zm)>;
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paulwalker-arm wrote:

The AArch64ExpandPseudoInsts route is more in keeping with how we normally solve this problem for SVE.  Whereby we have a BSLN_ZZZZ pseudo instructions that's converted into a (potentially movpfrx'd) BSL1N_ZZZZ or BSL2N_ZZZZ instruction based on the allocated registers.

https://github.com/llvm/llvm-project/pull/184847