[llvm] [AArch64] Model late forwarding in Neoverse N1 (PR #177590)

[Amina Chabane via llvm-commits]

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@@ -261,6 +261,48 @@ def N1Write_9c_6L_6V : SchedWriteRes<[N1UnitL, N1UnitL, N1UnitL,
                                       N1UnitV, N1UnitV, N1UnitV,
                                       N1UnitV, N1UnitV, N1UnitV]>;
 
+//===----------------------------------------------------------------------===//
+// Define forwarded types
+
+def N1Wr_IM32 : SchedWriteRes<[N1UnitM]> { let Latency = 2; }
+def N1Wr_IM64 : SchedWriteRes<[N1UnitM]> { let Latency = 4;
+                                           let ReleaseAtCycles = [3]; }
+def N1Rd_IMA  : SchedReadAdvance<1, [N1Wr_IM32, N1Wr_IM64]>;
+
+def N1Wr_FMA : SchedWriteRes<[N1UnitV]> { let Latency = 4; }
+def N1Rd_FMA : SchedReadAdvance<2, [WriteFMul, N1Wr_FMA]>;
+
+def N1Wr_VA : SchedWriteRes<[N1UnitV1]> { let Latency = 4; }
+def N1Rd_VA : SchedReadAdvance<3, [N1Wr_VA]>;
+
+def N1Wr_VMA  : SchedWriteRes<[N1UnitV0]> { let Latency = 4; }
+def N1Wr_VMAQ : SchedWriteRes<[N1UnitV0, N1UnitV0]> { let Latency = 5;
+                                                      let NumMicroOps = 2; }
+def N1Rd_VMA  : SchedReadAdvance<3, [N1Wr_VMA, N1Wr_VMAQ]>;
+
+def N1Wr_VMAL : SchedWriteRes<[N1UnitV0]> { let Latency = 4; }
+def N1Rd_VMAL : SchedReadAdvance<3, [N1Wr_VMAL]>;
+
+def N1Wr_VPA : SchedWriteRes<[N1UnitV1]> { let Latency = 4; }
+def N1Rd_VPA : SchedReadAdvance<3, [N1Wr_VPA]>;
+
+def N1Wr_VSA : SchedWriteRes<[N1UnitV1]> { let Latency = 4; }
+def N1Rd_VSA : SchedReadAdvance<3, [N1Wr_VSA]>;
+
+def N1Wr_VFM  : SchedWriteRes<[N1UnitV]> { let Latency = 3; }
+def N1Wr_VFMA : SchedWriteRes<[N1UnitV]> { let Latency = 4; }
+def N1Rd_VFMA : SchedReadAdvance<2, [N1Wr_VFM, N1Wr_VFMA]>;
+
+def N1Wr_VFMAL : SchedWriteRes<[N1UnitV]> { let Latency = 5; }
+def N1Rd_VFMAL : SchedReadAdvance<3, [N1Wr_VFMAL]>;
+
+def N1Wr_CRC : SchedWriteRes<[N1UnitM]> { let Latency = 2; }
+def N1Rd_CRC : SchedReadAdvance<1, [N1Wr_CRC]>;
+
+def N1Wr_MH   : SchedWriteRes<[N1UnitM]> { let Latency = 5;
+                                           let ReleaseAtCycles = [4]; }
+def N1Rd_MH : SchedReadAdvance<2, [N1Wr_MH]>;
----------------
Amichaxx wrote:

Done, thanks for reviewing!

https://github.com/llvm/llvm-project/pull/177590