[llvm] [RISCV][P-ext] Select plui.h/w and improve usage of pli.b/h/w. (PR #184937)
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Thu Mar 5 18:50:53 PST 2026
https://github.com/topperc updated https://github.com/llvm/llvm-project/pull/184937
>From d009645bf46c7ec84d8d251a81c12d1aa6c4c983 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Thu, 5 Mar 2026 15:05:51 -0800
Subject: [PATCH 1/4] [RISCV][P-ext] Select (splat_vector 0) as copy from X0.
---
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp | 16 ++++++++++++++++
llvm/test/CodeGen/RISCV/rvp-ext-rv32.ll | 3 +--
llvm/test/CodeGen/RISCV/rvp-ext-rv64.ll | 3 +--
3 files changed, 18 insertions(+), 4 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index 6387ab998d7b8..a24592a2bd5fa 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -2868,6 +2868,22 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
}
break;
}
+ case ISD::SPLAT_VECTOR: {
+ if (!Subtarget->hasStdExtP())
+ break;
+ auto *ConstNode = dyn_cast<ConstantSDNode>(Node->getOperand(0));
+ if (!ConstNode)
+ break;
+
+ if (ConstNode->isZero()) {
+ SDValue New =
+ CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL, RISCV::X0, VT);
+ ReplaceNode(Node, New.getNode());
+ return;
+ }
+
+ break;
+ }
case ISD::SCALAR_TO_VECTOR:
if (Subtarget->hasStdExtP()) {
MVT SrcVT = Node->getOperand(0).getSimpleValueType();
diff --git a/llvm/test/CodeGen/RISCV/rvp-ext-rv32.ll b/llvm/test/CodeGen/RISCV/rvp-ext-rv32.ll
index b34130ac726fa..bdee7f0df0d30 100644
--- a/llvm/test/CodeGen/RISCV/rvp-ext-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvp-ext-rv32.ll
@@ -648,10 +648,9 @@ define <2 x i16> @test_psslai_h(<2 x i16> %a) {
define <4 x i8> @test_psslai_b(<4 x i8> %a) {
; CHECK-LABEL: test_psslai_b:
; CHECK: # %bb.0:
-; CHECK-NEXT: pli.b a1, 0
+; CHECK-NEXT: pmslt.b a1, a0, zero
; CHECK-NEXT: li a2, 128
; CHECK-NEXT: pli.b a3, 127
-; CHECK-NEXT: pmslt.b a1, a0, a1
; CHECK-NEXT: padd.bs a2, zero, a2
; CHECK-NEXT: merge a1, a3, a2
; CHECK-NEXT: pslli.b a2, a0, 2
diff --git a/llvm/test/CodeGen/RISCV/rvp-ext-rv64.ll b/llvm/test/CodeGen/RISCV/rvp-ext-rv64.ll
index e577700f1085b..e5c1650cbed33 100644
--- a/llvm/test/CodeGen/RISCV/rvp-ext-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvp-ext-rv64.ll
@@ -922,10 +922,9 @@ define <4 x i16> @test_psslai_h(<4 x i16> %a) {
define <8 x i8> @test_psslai_b(<8 x i8> %a) {
; CHECK-LABEL: test_psslai_b:
; CHECK: # %bb.0:
-; CHECK-NEXT: pli.b a1, 0
+; CHECK-NEXT: pmslt.b a1, a0, zero
; CHECK-NEXT: li a2, 128
; CHECK-NEXT: pli.b a3, 127
-; CHECK-NEXT: pmslt.b a1, a0, a1
; CHECK-NEXT: padd.bs a2, zero, a2
; CHECK-NEXT: merge a1, a3, a2
; CHECK-NEXT: pslli.b a2, a0, 2
>From 0bae302c1fe458801562e47db80f94419d413310 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Thu, 5 Mar 2026 17:02:13 -0800
Subject: [PATCH 2/4] Simplify tests
---
llvm/test/CodeGen/RISCV/rvp-ext-rv32.ll | 12 ++++--------
llvm/test/CodeGen/RISCV/rvp-ext-rv64.ll | 9 +++------
2 files changed, 7 insertions(+), 14 deletions(-)
diff --git a/llvm/test/CodeGen/RISCV/rvp-ext-rv32.ll b/llvm/test/CodeGen/RISCV/rvp-ext-rv32.ll
index bdee7f0df0d30..2f8d5e31fd735 100644
--- a/llvm/test/CodeGen/RISCV/rvp-ext-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvp-ext-rv32.ll
@@ -422,8 +422,7 @@ define <2 x i16> @test_pli_h() {
; CHECK: # %bb.0:
; CHECK-NEXT: pli.h a0, 42
; CHECK-NEXT: ret
- %res = add <2 x i16> <i16 42, i16 42>, <i16 0, i16 0>
- ret <2 x i16> %res
+ ret <2 x i16> splat (i16 42)
}
define <2 x i16> @test_pli_h_negative() {
@@ -431,8 +430,7 @@ define <2 x i16> @test_pli_h_negative() {
; CHECK: # %bb.0:
; CHECK-NEXT: pli.h a0, -5
; CHECK-NEXT: ret
- %res = add <2 x i16> <i16 -5, i16 -5>, <i16 0, i16 0>
- ret <2 x i16> %res
+ ret <2 x i16> splat (i16 -5)
}
; Test PLI for v4i8 with unsigned immediate
@@ -441,8 +439,7 @@ define <4 x i8> @test_pli_b() {
; CHECK: # %bb.0:
; CHECK-NEXT: pli.b a0, 32
; CHECK-NEXT: ret
- %res = add <4 x i8> <i8 32, i8 32, i8 32, i8 32>, <i8 0, i8 0, i8 0, i8 0>
- ret <4 x i8> %res
+ ret <4 x i8> splat (i8 32)
}
define <4 x i8> @test_pli_b_negative() {
@@ -450,8 +447,7 @@ define <4 x i8> @test_pli_b_negative() {
; CHECK: # %bb.0:
; CHECK-NEXT: pli.b a0, -2
; CHECK-NEXT: ret
- %res = add <4 x i8> <i8 -2, i8 -2, i8 -2, i8 -2>, <i8 0, i8 0, i8 0, i8 0>
- ret <4 x i8> %res
+ ret <4 x i8> splat (i8 -2)
}
define i16 @test_extract_vector_16(<2 x i16> %a) {
diff --git a/llvm/test/CodeGen/RISCV/rvp-ext-rv64.ll b/llvm/test/CodeGen/RISCV/rvp-ext-rv64.ll
index e5c1650cbed33..70277062a4d35 100644
--- a/llvm/test/CodeGen/RISCV/rvp-ext-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvp-ext-rv64.ll
@@ -518,8 +518,7 @@ define <4 x i16> @test_pli_h() {
; CHECK: # %bb.0:
; CHECK-NEXT: pli.h a0, 100
; CHECK-NEXT: ret
- %res = add <4 x i16> <i16 100, i16 100, i16 100, i16 100>, <i16 0, i16 0, i16 0, i16 0>
- ret <4 x i16> %res
+ ret <4 x i16> splat (i16 100)
}
; Test PLI for v8i8 with unsigned immediate
@@ -528,8 +527,7 @@ define <8 x i8> @test_pli_b() {
; CHECK: # %bb.0:
; CHECK-NEXT: pli.b a0, 64
; CHECK-NEXT: ret
- %res = add <8 x i8> <i8 64, i8 64, i8 64, i8 64, i8 64, i8 64, i8 64, i8 64>, <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
- ret <8 x i8> %res
+ ret <8 x i8> splat (i8 64)
}
; Test PLI for v2i32 with signed immediate
@@ -538,8 +536,7 @@ define <2 x i32> @test_pli_w() {
; CHECK: # %bb.0:
; CHECK-NEXT: pli.w a0, -256
; CHECK-NEXT: ret
- %res = add <2 x i32> <i32 -256, i32 -256>, <i32 0, i32 0>
- ret <2 x i32> %res
+ ret <2 x i32> splat (i32 -256)
}
define i16 @test_extract_vector_16(<4 x i16> %a) {
>From 8817a32114652257b207f8dfa0032ca973909f6b Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Thu, 5 Mar 2026 17:17:38 -0800
Subject: [PATCH 3/4] Pre-commit tests
---
llvm/test/CodeGen/RISCV/rvp-ext-rv32.ll | 46 ++++++++++-
llvm/test/CodeGen/RISCV/rvp-ext-rv64.ll | 100 ++++++++++++++++++++++--
2 files changed, 136 insertions(+), 10 deletions(-)
diff --git a/llvm/test/CodeGen/RISCV/rvp-ext-rv32.ll b/llvm/test/CodeGen/RISCV/rvp-ext-rv32.ll
index 2f8d5e31fd735..6cff3c2ce3212 100644
--- a/llvm/test/CodeGen/RISCV/rvp-ext-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvp-ext-rv32.ll
@@ -442,6 +442,16 @@ define <4 x i8> @test_pli_b() {
ret <4 x i8> splat (i8 32)
}
+define <2 x i16> @test_pli_b_v2i16() {
+; CHECK-LABEL: test_pli_b_v2i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a0, 2
+; CHECK-NEXT: addi a0, a0, 32
+; CHECK-NEXT: padd.hs a0, zero, a0
+; CHECK-NEXT: ret
+ ret <2 x i16> splat (i16 u0x2020)
+}
+
define <4 x i8> @test_pli_b_negative() {
; CHECK-LABEL: test_pli_b_negative:
; CHECK: # %bb.0:
@@ -450,6 +460,34 @@ define <4 x i8> @test_pli_b_negative() {
ret <4 x i8> splat (i8 -2)
}
+define <2 x i16> @test_pli_b_negative_v2i16() {
+; CHECK-LABEL: test_pli_b_negative_v2i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pli.h a0, -258
+; CHECK-NEXT: ret
+ ret <2 x i16> splat (i16 u0xfefe)
+}
+
+define <2 x i16> @test_plui_h() {
+; CHECK-LABEL: test_plui_h:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a0, 3
+; CHECK-NEXT: addi a0, a0, 1664
+; CHECK-NEXT: padd.hs a0, zero, a0
+; CHECK-NEXT: ret
+ ret <2 x i16> splat (i16 u0x3680)
+}
+
+define <2 x i16> @test_plui_h_negative() {
+; CHECK-LABEL: test_plui_h_negative:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a0, 1048571
+; CHECK-NEXT: addi a0, a0, 1600
+; CHECK-NEXT: padd.hs a0, zero, a0
+; CHECK-NEXT: ret
+ ret <2 x i16> splat (i16 u0xb640)
+}
+
define i16 @test_extract_vector_16(<2 x i16> %a) {
; CHECK-LABEL: test_extract_vector_16:
; CHECK: # %bb.0:
@@ -1713,10 +1751,10 @@ define <2 x i16> @test_select_v2i16(i1 %cond, <2 x i16> %a, <2 x i16> %b) {
; CHECK: # %bb.0:
; CHECK-NEXT: andi a3, a0, 1
; CHECK-NEXT: mv a0, a1
-; CHECK-NEXT: bnez a3, .LBB120_2
+; CHECK-NEXT: bnez a3, .LBB124_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a0, a2
-; CHECK-NEXT: .LBB120_2:
+; CHECK-NEXT: .LBB124_2:
; CHECK-NEXT: ret
%res = select i1 %cond, <2 x i16> %a, <2 x i16> %b
ret <2 x i16> %res
@@ -1727,10 +1765,10 @@ define <4 x i8> @test_select_v4i8(i1 %cond, <4 x i8> %a, <4 x i8> %b) {
; CHECK: # %bb.0:
; CHECK-NEXT: andi a3, a0, 1
; CHECK-NEXT: mv a0, a1
-; CHECK-NEXT: bnez a3, .LBB121_2
+; CHECK-NEXT: bnez a3, .LBB125_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a0, a2
-; CHECK-NEXT: .LBB121_2:
+; CHECK-NEXT: .LBB125_2:
; CHECK-NEXT: ret
%res = select i1 %cond, <4 x i8> %a, <4 x i8> %b
ret <4 x i8> %res
diff --git a/llvm/test/CodeGen/RISCV/rvp-ext-rv64.ll b/llvm/test/CodeGen/RISCV/rvp-ext-rv64.ll
index 70277062a4d35..32f1fdde6e1f9 100644
--- a/llvm/test/CodeGen/RISCV/rvp-ext-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvp-ext-rv64.ll
@@ -521,6 +521,16 @@ define <4 x i16> @test_pli_h() {
ret <4 x i16> splat (i16 100)
}
+define <2 x i32> @test_pli_h_v2i32() {
+; CHECK-LABEL: test_pli_h_v2i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a0, 6
+; CHECK-NEXT: addi a0, a0, 1124
+; CHECK-NEXT: padd.ws a0, zero, a0
+; CHECK-NEXT: ret
+ ret <2 x i32> splat (i32 u0x640064)
+}
+
; Test PLI for v8i8 with unsigned immediate
define <8 x i8> @test_pli_b() {
; CHECK-LABEL: test_pli_b:
@@ -530,6 +540,26 @@ define <8 x i8> @test_pli_b() {
ret <8 x i8> splat (i8 64)
}
+define <4 x i16> @test_pli_b_v4i16() {
+; CHECK-LABEL: test_pli_b_v4i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a0, 4
+; CHECK-NEXT: addi a0, a0, 64
+; CHECK-NEXT: padd.hs a0, zero, a0
+; CHECK-NEXT: ret
+ ret <4 x i16> splat (i16 u0x4040)
+}
+
+define <2 x i32> @test_pli_b_v2i32() {
+; CHECK-LABEL: test_pli_b_v2i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a0, 263172
+; CHECK-NEXT: addi a0, a0, 64
+; CHECK-NEXT: padd.ws a0, zero, a0
+; CHECK-NEXT: ret
+ ret <2 x i32> splat (i32 u0x40404040)
+}
+
; Test PLI for v2i32 with signed immediate
define <2 x i32> @test_pli_w() {
; CHECK-LABEL: test_pli_w:
@@ -539,6 +569,64 @@ define <2 x i32> @test_pli_w() {
ret <2 x i32> splat (i32 -256)
}
+define <4 x i16> @test_plui_h() {
+; CHECK-LABEL: test_plui_h:
+; CHECK: # %bb.0:
+; CHECK-NEXT: li a0, 25
+; CHECK-NEXT: slli a0, a0, 8
+; CHECK-NEXT: padd.hs a0, zero, a0
+; CHECK-NEXT: ret
+ ret <4 x i16> splat (i16 u0x1900)
+}
+
+define <4 x i16> @test_plui_h_negative() {
+; CHECK-LABEL: test_plui_h_negative:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a0, 1048570
+; CHECK-NEXT: addi a0, a0, -1792
+; CHECK-NEXT: padd.hs a0, zero, a0
+; CHECK-NEXT: ret
+ ret <4 x i16> splat (i16 u0x9900)
+}
+
+define <2 x i32> @test_plui_h_v2i32() {
+; CHECK-LABEL: test_plui_h_v2i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a0, 102402
+; CHECK-NEXT: addi a0, a0, -1792
+; CHECK-NEXT: padd.ws a0, zero, a0
+; CHECK-NEXT: ret
+ ret <2 x i32> splat (i32 u0x19001900)
+}
+
+define <2 x i32> @test_plui_h_negative_v2i32() {
+; CHECK-LABEL: test_plui_h_negative_v2i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a0, 626698
+; CHECK-NEXT: addi a0, a0, -1792
+; CHECK-NEXT: padd.ws a0, zero, a0
+; CHECK-NEXT: ret
+ ret <2 x i32> splat (i32 u0x99009900)
+}
+
+define <2 x i32> @test_plui_w() {
+; CHECK-LABEL: test_plui_w:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a0, 76800
+; CHECK-NEXT: padd.ws a0, zero, a0
+; CHECK-NEXT: ret
+ ret <2 x i32> splat (i32 u0x12c00000)
+}
+
+define <2 x i32> @test_plui_w_negative() {
+; CHECK-LABEL: test_plui_w_negative:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a0, 825344
+; CHECK-NEXT: padd.ws a0, zero, a0
+; CHECK-NEXT: ret
+ ret <2 x i32> splat (i32 u0xc9800000)
+}
+
define i16 @test_extract_vector_16(<4 x i16> %a) {
; CHECK-LABEL: test_extract_vector_16:
; CHECK: # %bb.0:
@@ -2059,10 +2147,10 @@ define <4 x i16> @test_select_v4i16(i1 %cond, <4 x i16> %a, <4 x i16> %b) {
; CHECK: # %bb.0:
; CHECK-NEXT: andi a3, a0, 1
; CHECK-NEXT: mv a0, a1
-; CHECK-NEXT: bnez a3, .LBB165_2
+; CHECK-NEXT: bnez a3, .LBB174_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a0, a2
-; CHECK-NEXT: .LBB165_2:
+; CHECK-NEXT: .LBB174_2:
; CHECK-NEXT: ret
%res = select i1 %cond, <4 x i16> %a, <4 x i16> %b
ret <4 x i16> %res
@@ -2073,10 +2161,10 @@ define <8 x i8> @test_select_v8i8(i1 %cond, <8 x i8> %a, <8 x i8> %b) {
; CHECK: # %bb.0:
; CHECK-NEXT: andi a3, a0, 1
; CHECK-NEXT: mv a0, a1
-; CHECK-NEXT: bnez a3, .LBB166_2
+; CHECK-NEXT: bnez a3, .LBB175_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a0, a2
-; CHECK-NEXT: .LBB166_2:
+; CHECK-NEXT: .LBB175_2:
; CHECK-NEXT: ret
%res = select i1 %cond, <8 x i8> %a, <8 x i8> %b
ret <8 x i8> %res
@@ -2087,10 +2175,10 @@ define <2 x i32> @test_select_v2i32(i1 %cond, <2 x i32> %a, <2 x i32> %b) {
; CHECK: # %bb.0:
; CHECK-NEXT: andi a3, a0, 1
; CHECK-NEXT: mv a0, a1
-; CHECK-NEXT: bnez a3, .LBB167_2
+; CHECK-NEXT: bnez a3, .LBB176_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a0, a2
-; CHECK-NEXT: .LBB167_2:
+; CHECK-NEXT: .LBB176_2:
; CHECK-NEXT: ret
%res = select i1 %cond, <2 x i32> %a, <2 x i32> %b
ret <2 x i32> %res
>From ef1cc39f49a2660451065351f23dfc9f73a34ef5 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Thu, 5 Mar 2026 18:22:50 -0800
Subject: [PATCH 4/4] [RISCV][P-ext] Select plui.h/w and improve usage of
pli.b/h/w.
This patch adds custom instruction selection of splat_vector of
constants. Rather that using the element size from the VT, find
the smallest splat size in the constant. This allow us to use
pli.b for i16 or i32 elements that contain a byte splat.
---
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp | 32 ++++++++++++++++++
llvm/lib/Target/RISCV/RISCVInstrInfoP.td | 8 -----
llvm/test/CodeGen/RISCV/rvp-ext-rv32.ll | 17 +++-------
llvm/test/CodeGen/RISCV/rvp-ext-rv64.ll | 37 ++++++---------------
4 files changed, 47 insertions(+), 47 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index a24592a2bd5fa..5eec3a5ee458d 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -2882,6 +2882,38 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
return;
}
+ unsigned EltSize = VT.getVectorElementType().getSizeInBits();
+ APInt Val = ConstNode->getAPIntValue().trunc(EltSize);
+
+ // Find the smallest splat.
+ if (Val.getBitWidth() > 16 && Val.isSplat(16))
+ Val = Val.trunc(16);
+ if (Val.getBitWidth() > 8 && Val.isSplat(8))
+ Val = Val.trunc(8);
+
+ EltSize = Val.getBitWidth();
+ int64_t Imm = Val.getSExtValue();
+
+ unsigned Opc = 0;
+ if (EltSize == 8) {
+ Opc = RISCV::PLI_B;
+ } else if (isInt<10>(Imm)) {
+ Opc = EltSize == 32 ? RISCV::PLI_W : RISCV::PLI_H;
+ } else if (EltSize == 16 && (Imm & 0x3f) == 0) {
+ Opc = RISCV::PLUI_H;
+ Imm = Imm >> 10;
+ } else if (EltSize == 32 && (Imm & 0x3fffff) == 0) {
+ Opc = RISCV::PLUI_W;
+ Imm = Imm >> 22;
+ }
+
+ if (Opc) {
+ SDNode *NewNode = CurDAG->getMachineNode(
+ Opc, DL, VT, CurDAG->getSignedTargetConstant(Imm, DL, XLenVT));
+ ReplaceNode(Node, NewNode);
+ return;
+ }
+
break;
}
case ISD::SCALAR_TO_VECTOR:
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoP.td b/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
index 2e8e4c9fd816a..1642ce4c5dda2 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
@@ -1816,11 +1816,6 @@ let Predicates = [HasStdExtP] in {
def: Pat<(XLenVecI16VT (riscv_psra GPR:$rs1, GPR:$rs2)),
(PSRA_HS GPR:$rs1, GPR:$rs2)>;
- // 8-bit PLI SD node pattern
- def: Pat<(XLenVecI8VT (splat_vector simm8_unsigned:$imm8)), (PLI_B simm8_unsigned:$imm8)>;
- // 16-bit PLI SD node pattern
- def: Pat<(XLenVecI16VT (splat_vector simm10:$imm10)), (PLI_H simm10:$imm10)>;
-
// // splat pattern
def: Pat<(XLenVecI8VT (splat_vector (XLenVT GPR:$rs2))), (PADD_BS (XLenVT X0), GPR:$rs2)>;
def: Pat<(XLenVecI16VT (splat_vector (XLenVT GPR:$rs2))), (PADD_HS (XLenVT X0), GPR:$rs2)>;
@@ -1924,9 +1919,6 @@ let Predicates = [HasStdExtP, IsRV64] in {
(PPAIRE_H zexti16:$rs1,
(XLenVT (PPAIRE_B zexti8:$op1rs1, GPR:$op1rs2)))>;
- // 32-bit PLI SD node pattern
- def: Pat<(v2i32 (splat_vector simm10:$imm10)), (PLI_W simm10:$imm10)>;
-
// Basic 32-bit arithmetic patterns
def: Pat<(v2i32 (add GPR:$rs1, GPR:$rs2)), (PADD_W GPR:$rs1, GPR:$rs2)>;
def: Pat<(v2i32 (sub GPR:$rs1, GPR:$rs2)), (PSUB_W GPR:$rs1, GPR:$rs2)>;
diff --git a/llvm/test/CodeGen/RISCV/rvp-ext-rv32.ll b/llvm/test/CodeGen/RISCV/rvp-ext-rv32.ll
index 6cff3c2ce3212..b5fa1225a4f17 100644
--- a/llvm/test/CodeGen/RISCV/rvp-ext-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvp-ext-rv32.ll
@@ -445,9 +445,7 @@ define <4 x i8> @test_pli_b() {
define <2 x i16> @test_pli_b_v2i16() {
; CHECK-LABEL: test_pli_b_v2i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: lui a0, 2
-; CHECK-NEXT: addi a0, a0, 32
-; CHECK-NEXT: padd.hs a0, zero, a0
+; CHECK-NEXT: pli.b a0, 32
; CHECK-NEXT: ret
ret <2 x i16> splat (i16 u0x2020)
}
@@ -463,7 +461,7 @@ define <4 x i8> @test_pli_b_negative() {
define <2 x i16> @test_pli_b_negative_v2i16() {
; CHECK-LABEL: test_pli_b_negative_v2i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: pli.h a0, -258
+; CHECK-NEXT: pli.b a0, -2
; CHECK-NEXT: ret
ret <2 x i16> splat (i16 u0xfefe)
}
@@ -471,9 +469,7 @@ define <2 x i16> @test_pli_b_negative_v2i16() {
define <2 x i16> @test_plui_h() {
; CHECK-LABEL: test_plui_h:
; CHECK: # %bb.0:
-; CHECK-NEXT: lui a0, 3
-; CHECK-NEXT: addi a0, a0, 1664
-; CHECK-NEXT: padd.hs a0, zero, a0
+; CHECK-NEXT: plui.h a0, 13
; CHECK-NEXT: ret
ret <2 x i16> splat (i16 u0x3680)
}
@@ -481,9 +477,7 @@ define <2 x i16> @test_plui_h() {
define <2 x i16> @test_plui_h_negative() {
; CHECK-LABEL: test_plui_h_negative:
; CHECK: # %bb.0:
-; CHECK-NEXT: lui a0, 1048571
-; CHECK-NEXT: addi a0, a0, 1600
-; CHECK-NEXT: padd.hs a0, zero, a0
+; CHECK-NEXT: plui.h a0, -19
; CHECK-NEXT: ret
ret <2 x i16> splat (i16 u0xb640)
}
@@ -683,9 +677,8 @@ define <4 x i8> @test_psslai_b(<4 x i8> %a) {
; CHECK-LABEL: test_psslai_b:
; CHECK: # %bb.0:
; CHECK-NEXT: pmslt.b a1, a0, zero
-; CHECK-NEXT: li a2, 128
+; CHECK-NEXT: pli.b a2, -128
; CHECK-NEXT: pli.b a3, 127
-; CHECK-NEXT: padd.bs a2, zero, a2
; CHECK-NEXT: merge a1, a3, a2
; CHECK-NEXT: pslli.b a2, a0, 2
; CHECK-NEXT: psrai.b a3, a2, 2
diff --git a/llvm/test/CodeGen/RISCV/rvp-ext-rv64.ll b/llvm/test/CodeGen/RISCV/rvp-ext-rv64.ll
index 32f1fdde6e1f9..82a5378ff6174 100644
--- a/llvm/test/CodeGen/RISCV/rvp-ext-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvp-ext-rv64.ll
@@ -524,9 +524,7 @@ define <4 x i16> @test_pli_h() {
define <2 x i32> @test_pli_h_v2i32() {
; CHECK-LABEL: test_pli_h_v2i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: lui a0, 6
-; CHECK-NEXT: addi a0, a0, 1124
-; CHECK-NEXT: padd.ws a0, zero, a0
+; CHECK-NEXT: pli.h a0, 100
; CHECK-NEXT: ret
ret <2 x i32> splat (i32 u0x640064)
}
@@ -543,9 +541,7 @@ define <8 x i8> @test_pli_b() {
define <4 x i16> @test_pli_b_v4i16() {
; CHECK-LABEL: test_pli_b_v4i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: lui a0, 4
-; CHECK-NEXT: addi a0, a0, 64
-; CHECK-NEXT: padd.hs a0, zero, a0
+; CHECK-NEXT: pli.b a0, 64
; CHECK-NEXT: ret
ret <4 x i16> splat (i16 u0x4040)
}
@@ -553,9 +549,7 @@ define <4 x i16> @test_pli_b_v4i16() {
define <2 x i32> @test_pli_b_v2i32() {
; CHECK-LABEL: test_pli_b_v2i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: lui a0, 263172
-; CHECK-NEXT: addi a0, a0, 64
-; CHECK-NEXT: padd.ws a0, zero, a0
+; CHECK-NEXT: pli.b a0, 64
; CHECK-NEXT: ret
ret <2 x i32> splat (i32 u0x40404040)
}
@@ -572,9 +566,7 @@ define <2 x i32> @test_pli_w() {
define <4 x i16> @test_plui_h() {
; CHECK-LABEL: test_plui_h:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a0, 25
-; CHECK-NEXT: slli a0, a0, 8
-; CHECK-NEXT: padd.hs a0, zero, a0
+; CHECK-NEXT: plui.h a0, 6
; CHECK-NEXT: ret
ret <4 x i16> splat (i16 u0x1900)
}
@@ -582,9 +574,7 @@ define <4 x i16> @test_plui_h() {
define <4 x i16> @test_plui_h_negative() {
; CHECK-LABEL: test_plui_h_negative:
; CHECK: # %bb.0:
-; CHECK-NEXT: lui a0, 1048570
-; CHECK-NEXT: addi a0, a0, -1792
-; CHECK-NEXT: padd.hs a0, zero, a0
+; CHECK-NEXT: plui.h a0, -26
; CHECK-NEXT: ret
ret <4 x i16> splat (i16 u0x9900)
}
@@ -592,9 +582,7 @@ define <4 x i16> @test_plui_h_negative() {
define <2 x i32> @test_plui_h_v2i32() {
; CHECK-LABEL: test_plui_h_v2i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: lui a0, 102402
-; CHECK-NEXT: addi a0, a0, -1792
-; CHECK-NEXT: padd.ws a0, zero, a0
+; CHECK-NEXT: plui.h a0, 6
; CHECK-NEXT: ret
ret <2 x i32> splat (i32 u0x19001900)
}
@@ -602,9 +590,7 @@ define <2 x i32> @test_plui_h_v2i32() {
define <2 x i32> @test_plui_h_negative_v2i32() {
; CHECK-LABEL: test_plui_h_negative_v2i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: lui a0, 626698
-; CHECK-NEXT: addi a0, a0, -1792
-; CHECK-NEXT: padd.ws a0, zero, a0
+; CHECK-NEXT: plui.h a0, -26
; CHECK-NEXT: ret
ret <2 x i32> splat (i32 u0x99009900)
}
@@ -612,8 +598,7 @@ define <2 x i32> @test_plui_h_negative_v2i32() {
define <2 x i32> @test_plui_w() {
; CHECK-LABEL: test_plui_w:
; CHECK: # %bb.0:
-; CHECK-NEXT: lui a0, 76800
-; CHECK-NEXT: padd.ws a0, zero, a0
+; CHECK-NEXT: plui.w a0, 75
; CHECK-NEXT: ret
ret <2 x i32> splat (i32 u0x12c00000)
}
@@ -621,8 +606,7 @@ define <2 x i32> @test_plui_w() {
define <2 x i32> @test_plui_w_negative() {
; CHECK-LABEL: test_plui_w_negative:
; CHECK: # %bb.0:
-; CHECK-NEXT: lui a0, 825344
-; CHECK-NEXT: padd.ws a0, zero, a0
+; CHECK-NEXT: plui.w a0, -218
; CHECK-NEXT: ret
ret <2 x i32> splat (i32 u0xc9800000)
}
@@ -1008,9 +992,8 @@ define <8 x i8> @test_psslai_b(<8 x i8> %a) {
; CHECK-LABEL: test_psslai_b:
; CHECK: # %bb.0:
; CHECK-NEXT: pmslt.b a1, a0, zero
-; CHECK-NEXT: li a2, 128
+; CHECK-NEXT: pli.b a2, -128
; CHECK-NEXT: pli.b a3, 127
-; CHECK-NEXT: padd.bs a2, zero, a2
; CHECK-NEXT: merge a1, a3, a2
; CHECK-NEXT: pslli.b a2, a0, 2
; CHECK-NEXT: psrai.b a3, a2, 2
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