[llvm] [RISCV][P-ext] Support vector ISD::ABS using PABD instructions. (PR #184822)
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Thu Mar 5 13:47:35 PST 2026
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-risc-v
Author: Craig Topper (topperc)
<details>
<summary>Changes</summary>
---
Full diff: https://github.com/llvm/llvm-project/pull/184822.diff
4 Files Affected:
- (modified) llvm/lib/Target/RISCV/RISCVISelLowering.cpp (+1-1)
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfoP.td (+2)
- (modified) llvm/test/CodeGen/RISCV/rvp-ext-rv32.ll (+22-4)
- (modified) llvm/test/CodeGen/RISCV/rvp-ext-rv64.ll (+35-6)
``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 5c4b1f3a4bdc8..b797054b89833 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -576,7 +576,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
setOperationAction({ISD::AVGFLOORS, ISD::AVGFLOORU}, VTs, Legal);
for (MVT VT : VTs) {
if (VT != MVT::v2i32)
- setOperationAction({ISD::ABDS, ISD::ABDU}, VT, Legal);
+ setOperationAction({ISD::ABS, ISD::ABDS, ISD::ABDU}, VT, Legal);
if (VT.getVectorElementType() != MVT::i8)
setOperationAction(ISD::SSHLSAT, VT, Legal);
}
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoP.td b/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
index 2e8e4c9fd816a..c45a93f764913 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
@@ -1755,10 +1755,12 @@ let Predicates = [HasStdExtP] in {
def: Pat<(XLenVecI16VT (riscv_asubu GPR:$rs1, GPR:$rs2)), (PASUBU_H GPR:$rs1, GPR:$rs2)>;
// 8-bit absolute difference patterns
+ def: Pat<(XLenVecI8VT (abs GPR:$rs1)), (PABD_B GPR:$rs1, (XLenVecI8VT X0))>;
def: Pat<(XLenVecI8VT (abds GPR:$rs1, GPR:$rs2)), (PABD_B GPR:$rs1, GPR:$rs2)>;
def: Pat<(XLenVecI8VT (abdu GPR:$rs1, GPR:$rs2)), (PABDU_B GPR:$rs1, GPR:$rs2)>;
// 16-bit absolute difference patterns
+ def: Pat<(XLenVecI16VT (abs GPR:$rs1)), (PABD_H GPR:$rs1, (XLenVecI16VT X0))>;
def: Pat<(XLenVecI16VT (abds GPR:$rs1, GPR:$rs2)), (PABD_H GPR:$rs1, GPR:$rs2)>;
def: Pat<(XLenVecI16VT (abdu GPR:$rs1, GPR:$rs2)), (PABDU_H GPR:$rs1, GPR:$rs2)>;
diff --git a/llvm/test/CodeGen/RISCV/rvp-ext-rv32.ll b/llvm/test/CodeGen/RISCV/rvp-ext-rv32.ll
index b34130ac726fa..db5efa275e1b7 100644
--- a/llvm/test/CodeGen/RISCV/rvp-ext-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvp-ext-rv32.ll
@@ -310,6 +310,24 @@ define <4 x i8> @test_paaddu_b(<4 x i8> %a, <4 x i8> %b) {
ret <4 x i8> %res
}
+define <2 x i16> @test_pabs_h(<2 x i16> %a) {
+; CHECK-LABEL: test_pabs_h:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pabd.h a0, a0, zero
+; CHECK-NEXT: ret
+ %res = call <2 x i16> @llvm.abs.v2i16(<2 x i16> %a, i1 0)
+ ret <2 x i16> %res
+}
+
+define <4 x i8> @test_pabs_b(<4 x i8> %a) {
+; CHECK-LABEL: test_pabs_b:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pabd.b a0, a0, zero
+; CHECK-NEXT: ret
+ %res = call <4 x i8> @llvm.abs.v4i8(<4 x i8> %a, i1 0)
+ ret <4 x i8> %res
+}
+
; Test absolute difference signed for v2i16
define <2 x i16> @test_pdif_h(<2 x i16> %a, <2 x i16> %b) {
; CHECK-LABEL: test_pdif_h:
@@ -1718,10 +1736,10 @@ define <2 x i16> @test_select_v2i16(i1 %cond, <2 x i16> %a, <2 x i16> %b) {
; CHECK: # %bb.0:
; CHECK-NEXT: andi a3, a0, 1
; CHECK-NEXT: mv a0, a1
-; CHECK-NEXT: bnez a3, .LBB120_2
+; CHECK-NEXT: bnez a3, .LBB122_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a0, a2
-; CHECK-NEXT: .LBB120_2:
+; CHECK-NEXT: .LBB122_2:
; CHECK-NEXT: ret
%res = select i1 %cond, <2 x i16> %a, <2 x i16> %b
ret <2 x i16> %res
@@ -1732,10 +1750,10 @@ define <4 x i8> @test_select_v4i8(i1 %cond, <4 x i8> %a, <4 x i8> %b) {
; CHECK: # %bb.0:
; CHECK-NEXT: andi a3, a0, 1
; CHECK-NEXT: mv a0, a1
-; CHECK-NEXT: bnez a3, .LBB121_2
+; CHECK-NEXT: bnez a3, .LBB123_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a0, a2
-; CHECK-NEXT: .LBB121_2:
+; CHECK-NEXT: .LBB123_2:
; CHECK-NEXT: ret
%res = select i1 %cond, <4 x i8> %a, <4 x i8> %b
ret <4 x i8> %res
diff --git a/llvm/test/CodeGen/RISCV/rvp-ext-rv64.ll b/llvm/test/CodeGen/RISCV/rvp-ext-rv64.ll
index e577700f1085b..1c1e14afbc9bb 100644
--- a/llvm/test/CodeGen/RISCV/rvp-ext-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvp-ext-rv64.ll
@@ -374,6 +374,35 @@ define <8 x i8> @test_paaddu_b(<8 x i8> %a, <8 x i8> %b) {
ret <8 x i8> %res
}
+define <2 x i32> @test_pabs_w(<2 x i32> %a) {
+; CHECK-LABEL: test_pabs_w:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pli.w a1, 0
+; CHECK-NEXT: psub.w a1, a1, a0
+; CHECK-NEXT: pmax.w a0, a0, a1
+; CHECK-NEXT: ret
+ %res = call <2 x i32> @llvm.abs.v2i32(<2 x i32> %a, i1 0)
+ ret <2 x i32> %res
+}
+
+define <4 x i16> @test_pabs_h(<4 x i16> %a) {
+; CHECK-LABEL: test_pabs_h:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pabd.h a0, a0, zero
+; CHECK-NEXT: ret
+ %res = call <4 x i16> @llvm.abs.v4i16(<4 x i16> %a, i1 0)
+ ret <4 x i16> %res
+}
+
+define <8 x i8> @test_pabs_b(<8 x i8> %a) {
+; CHECK-LABEL: test_pabs_b:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pabd.b a0, a0, zero
+; CHECK-NEXT: ret
+ %res = call <8 x i8> @llvm.abs.v8i8(<8 x i8> %a, i1 0)
+ ret <8 x i8> %res
+}
+
; Test absolute difference signed for v2i32
; abds pattern: sub(smax(a,b), smin(a,b))
define <2 x i32> @test_pdif_w(<2 x i32> %a, <2 x i32> %b) {
@@ -2063,10 +2092,10 @@ define <4 x i16> @test_select_v4i16(i1 %cond, <4 x i16> %a, <4 x i16> %b) {
; CHECK: # %bb.0:
; CHECK-NEXT: andi a3, a0, 1
; CHECK-NEXT: mv a0, a1
-; CHECK-NEXT: bnez a3, .LBB165_2
+; CHECK-NEXT: bnez a3, .LBB168_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a0, a2
-; CHECK-NEXT: .LBB165_2:
+; CHECK-NEXT: .LBB168_2:
; CHECK-NEXT: ret
%res = select i1 %cond, <4 x i16> %a, <4 x i16> %b
ret <4 x i16> %res
@@ -2077,10 +2106,10 @@ define <8 x i8> @test_select_v8i8(i1 %cond, <8 x i8> %a, <8 x i8> %b) {
; CHECK: # %bb.0:
; CHECK-NEXT: andi a3, a0, 1
; CHECK-NEXT: mv a0, a1
-; CHECK-NEXT: bnez a3, .LBB166_2
+; CHECK-NEXT: bnez a3, .LBB169_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a0, a2
-; CHECK-NEXT: .LBB166_2:
+; CHECK-NEXT: .LBB169_2:
; CHECK-NEXT: ret
%res = select i1 %cond, <8 x i8> %a, <8 x i8> %b
ret <8 x i8> %res
@@ -2091,10 +2120,10 @@ define <2 x i32> @test_select_v2i32(i1 %cond, <2 x i32> %a, <2 x i32> %b) {
; CHECK: # %bb.0:
; CHECK-NEXT: andi a3, a0, 1
; CHECK-NEXT: mv a0, a1
-; CHECK-NEXT: bnez a3, .LBB167_2
+; CHECK-NEXT: bnez a3, .LBB170_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a0, a2
-; CHECK-NEXT: .LBB167_2:
+; CHECK-NEXT: .LBB170_2:
; CHECK-NEXT: ret
%res = select i1 %cond, <2 x i32> %a, <2 x i32> %b
ret <2 x i32> %res
``````````
</details>
https://github.com/llvm/llvm-project/pull/184822
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