[llvm] [AArch64] C1-Ultra Scheduling model (PR #182251)
Asher Dobrescu via llvm-commits
llvm-commits at lists.llvm.org
Thu Mar 5 09:09:17 PST 2026
================
@@ -0,0 +1,2034 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=aarch64 -mcpu=c1-ultra -mattr=+sve --instruction-info=0 --resource-pressure=0 --timeline --timeline-max-iterations=2 < %s | FileCheck %s
+
+# LLVM-MCA-BEGIN madd
+mul x0, x0, x0
+madd x0, x1, x2, x0
+madd x0, x1, x2, x0
+madd x0, x0, x0, x0
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN smaddl
+mul x0, x0, x0
+smaddl x0, w1, w2, x0
+smaddl x0, w1, w2, x0
+smaddl x0, w0, w0, x0
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN fmadd
+fadd d0, d0, d0
+fmadd d0, d1, d2, d0
+fmul d0, d0, d0
+fmadd d0, d1, d2, d0
+fmadd d0, d1, d2, d0
+fmadd d0, d0, d1, d2
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN saba
+mul v0.4s, v0.4s, v0.4s
+saba v0.4s, v1.4s, v2.4s
+saba v0.4s, v1.4s, v2.4s
+saba v0.4s, v0.4s, v1.4s
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN sdot
+mul v0.4s, v0.4s, v0.4s
+sdot v0.4s, v1.16b, v2.16b
+sdot v0.4s, v1.16b, v2.16b
+sdot v0.4s, v0.16b, v1.16b
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN smmla
+mul v0.4s, v0.4s, v0.4s
+smmla v0.4s, v1.16b, v2.16b
+smmla v0.4s, v1.16b, v2.16b
+smmla v0.4s, v0.16b, v1.16b
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN mla
+mul v0.4s, v0.4s, v0.4s
+mla v0.4s, v1.4s, v2.4s
+mla v0.4s, v1.4s, v2.4s
+mla v0.4s, v0.4s, v1.4s
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN sqrdmlah
+mul v0.4s, v0.4s, v0.4s
+sqrdmlah v0.8h, v1.8h, v2.8h
+sqrdmlah v0.8h, v1.8h, v2.8h
+sqrdmlah v0.8h, v1.8h, v2.8h
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN smlal2
+mul v0.4s, v0.4s, v0.4s
+smlal2 v0.4s, v1.8h, v2.8h
+smlal2 v0.4s, v1.8h, v2.8h
+smlal2 v0.4s, v0.8h, v1.8h
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN sqdmlal2
+mul v0.4s, v0.4s, v0.4s
+sqdmlal2 v0.4s, v1.8h, v2.8h
+sqdmlal2 v0.4s, v1.8h, v2.8h
+sqdmlal2 v0.4s, v1.8h, v2.8h
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN sadalp
+mul v0.4s, v0.4s, v0.4s
+sadalp v0.2d, v1.4s
+sadalp v0.2d, v1.4s
+sadalp v0.2d, v0.4s
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN fcmla
+fmul v0.4s, v0.4s, v0.4s
+fcmla v0.2d, v1.2d, v2.2d, #90
+fcmla v0.2d, v1.2d, v2.2d, #90
+fcmla v0.2d, v0.2d, v1.2d, #90
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN fmla
+fmul v0.2d, v0.2d, v0.2d
+fmla v0.2d, v1.2d, v2.2d
+fadd v0.2d, v0.2d, v0.2d
+fmla v0.2d, v1.2d, v2.2d
+fmla v0.2d, v1.2d, v2.2d
+fmla v0.2d, v0.2d, v1.2d
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN fmlal
+fmul v0.2d, v0.2d, v0.2d
+fmlal v0.4s, v1.4h, v2.4h
+fadd v0.2d, v0.2d, v0.2d
+fmlal v0.4s, v1.4h, v2.4h
+fmlal v0.4s, v1.4h, v2.4h
+fmlal v0.4s, v0.4h, v1.4h
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN bfdot
+fmul v0.2d, v0.2d, v0.2d
+bfdot v0.4s, v1.8h, v2.8h
+bfdot v0.4s, v1.8h, v2.8h
+bfdot v0.4s, v0.8h, v1.8h
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN bfmmla
+fmul v0.2d, v0.2d, v0.2d
+bfmmla v0.4s, v1.8h, v2.8h
+bfmmla v0.4s, v1.8h, v2.8h
+bfmmla v0.4s, v0.8h, v1.8h
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN bfmlalb
+fmul v0.2d, v0.2d, v0.2d
+bfmlalb v0.4s, v1.8h, v2.8h
+bfmlalb v0.4s, v1.8h, v2.8h
+bfmlalb v0.4s, v0.8h, v1.8h
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN crc32
+mul w0, w0, w0
+crc32cb w0, w0, w1
+crc32cb w0, w0, w1
+crc32cb w0, w0, w0
+crc32b w0, w0, w15
+crc32h w0, w0, w21
+crc32w w0, w0, w24
+crc32x w0, w0, x25
+crc32ch w0, w0, w16
+crc32cw w0, w0, w23
+crc32cx w0, w0, x5
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN Z saba
+mul z0.d, z0.d, z0.d
+saba z0.d, z1.d, z2.d
+saba z0.d, z1.d, z2.d
+saba z0.d, z0.d, z1.d
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN Z sabalt
+mul z0.h, z0.h, z0.h
+sabalt z0.h, z1.b, z2.b
+sabalt z0.h, z1.b, z2.b
+sabalt z0.h, z0.b, z1.b
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN Z sadalp
+mul z0.d, z0.d, z0.d
+sadalp z0.d, p0/m, z1.s
+sadalp z0.d, p0/m, z1.s
+sadalp z0.d, p0/m, z0.s
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN Z ssra
+mul z0.d, z0.d, z0.d
+ssra z0.d, z1.d, #1
+ssra z0.d, z1.d, #1
+ssra z0.d, z0.d, #1
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN Z cdot.s
+mul z0.d, z0.d, z0.d
+cdot z0.s, z1.b, z2.b, #90
+cdot z0.s, z1.b, z2.b, #90
+cdot z0.s, z0.b, z1.b, #90
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN Z cdot.d
+mul z0.d, z0.d, z0.d
+cdot z0.d, z1.h, z2.h, #90
+cdot z0.d, z1.h, z2.h, #90
+cdot z0.d, z0.h, z1.h, #90
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN Z cmla.b
+mul z0.d, z0.d, z0.d
+cmla z0.b, z1.b, z2.b, #90
+cmla z0.b, z1.b, z2.b, #90
+cmla z0.b, z0.b, z1.b, #90
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN Z cmla.d
+mul z0.d, z0.d, z0.d
+cmla z0.d, z1.d, z2.d, #90
+cmla z0.d, z1.d, z2.d, #90
+cmla z0.d, z0.d, z1.d, #90
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN Z sdot.s
+mul z0.d, p0/m, z0.d, z0.d
+sdot z0.s, z1.b, z2.b
+sdot z0.s, z1.b, z2.b
+sdot z0.s, z0.b, z1.b
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN Z sudot
+mul z0.d, p0/m, z0.d, z0.d
+sdot z0.s, z1.b, z2.b[1]
+sdot z0.s, z1.b, z2.b[1]
+sdot z0.s, z0.b, z1.b[1]
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN Z sdot.d
+mul z0.d, z0.d, z0.d
+sdot z0.d, z1.h, z2.h
+sdot z0.d, z1.h, z2.h
+sdot z0.d, z0.h, z1.h
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN Z smmla
+mul z0.s, z0.s, z0.s
+smmla z0.s, z1.b, z2.b
+smmla z0.s, z1.b, z2.b
+smmla z0.s, z0.b, z1.b
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN Z mla.b
+mul z0.d, z0.d, z0.d
+mla z0.b, p0/m, z1.b, z2.b
+mla z0.b, p0/m, z1.b, z2.b
+mla z0.b, p0/m, z0.b, z1.b
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN Z mla.d
+mul z0.d, z0.d, z0.d
+mla z0.d, p0/m, z1.d, z2.d
+mla z0.d, p0/m, z1.d, z2.d
+mla z0.d, p0/m, z0.d, z1.d
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN Z smlalb
+mul z0.d, z0.d, z0.d
+smlalb z0.d, z1.s, z2.s
+smlalb z0.d, z1.s, z2.s
+smlalb z0.d, z0.s, z1.s
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN Z sqdmlalb
+mul z0.d, z0.d, z0.d
+sqdmlalb z0.d, z1.s, z2.s
+sqdmlalb z0.d, z1.s, z2.s
+sqdmlalb z0.d, z0.s, z1.s
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN Z sqrdmlah.b
+mul z0.d, z0.d, z0.d
+sqrdmlah z0.b, z1.b, z2.b
+sqrdmlah z0.b, z1.b, z2.b
+sqrdmlah z0.b, z0.b, z1.b
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN Z sqrdmlah.d
+mul z0.d, z0.d, z0.d
+sqrdmlah z0.d, z1.d, z2.d
+sqrdmlah z0.d, z1.d, z2.d
+sqrdmlah z0.d, z0.d, z1.d
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN Z fcmla ZPmZZ
+fmul z0.d, z0.d, z0.d
+fcmla z0.d, p0/m, z1.d, z2.d, 90
+fcmla z0.d, p0/m, z1.d, z2.d, 90
+fcmla z0.d, p0/m, z0.d, z1.d, 90
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN Z fcmla ZZZI
+fmul z0.d, z0.d, z0.d
+fcmla z0.s, z1.s, z2.s[1], 90
+fcmla z0.s, z1.s, z2.s[1], 90
+fcmla z0.s, z0.s, z1.s[1], 90
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN Z fmla ZPmZZ
+fmul z0.d, z0.d, z0.d
+fmla z0.d, p0/m, z1.d, z2.d
+fmla z0.d, p0/m, z1.d, z2.d
+fmla z0.d, p0/m, z0.d, z1.d
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN Z fmla ZZZI
+fmul z0.d, z0.d, z0.d
+fmla z0.d, z1.d, z2.d[1]
+fmla z0.d, z1.d, z2.d[1]
+fmla z0.d, z0.d, z1.d[1]
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN Z fmlalb ZZZ
+fmul z0.d, z0.d, z0.d
+fmlalb z0.s, z1.h, z2.h
+fmlalb z0.s, z1.h, z2.h
+fmlalb z0.s, z0.h, z1.h
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN Z bfdot
+fmul z0.d, z0.d, z0.d
+bfdot z0.s, z1.h, z2.h
+bfdot z0.s, z1.h, z2.h
+bfdot z0.s, z0.h, z1.h
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN Z bfmmla
+fmul z0.d, z0.d, z0.d
+bfmmla z0.s, z1.h, z2.h
+bfmmla z0.s, z1.h, z2.h
+bfmmla z0.s, z0.h, z1.h
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN bfmlalb
+fmul z0.d, z0.d, z0.d
+bfmlalb z0.s, z1.h, z2.h
+bfmlalb z0.s, z1.h, z2.h
+bfmlalb z0.s, z0.h, z1.h
+# LLVM-MCA-END
+
+# CHECK: [0] Code Region - madd
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 400
+# CHECK-NEXT: Total Cycles: 1203
+# CHECK-NEXT: Total uOps: 400
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 0.33
+# CHECK-NEXT: IPC: 0.33
+# CHECK-NEXT: Block RThroughput: 1.0
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 0123456789
+# CHECK-NEXT: Index 0123456789 0123456
+
+# CHECK: [0,0] DeeeER . . . .. mul x0, x0, x0
+# CHECK-NEXT: [0,1] D===eeeER . . . .. madd x0, x1, x2, x0
+# CHECK-NEXT: [0,2] D======eeeER . . .. madd x0, x1, x2, x0
+# CHECK-NEXT: [0,3] D=========eeeER. . .. madd x0, x0, x0, x0
+# CHECK-NEXT: [1,0] D============eeeER . .. mul x0, x0, x0
+# CHECK-NEXT: [1,1] D===============eeeER .. madd x0, x1, x2, x0
+# CHECK-NEXT: [1,2] D==================eeeER .. madd x0, x1, x2, x0
+# CHECK-NEXT: [1,3] D=====================eeeER madd x0, x0, x0, x0
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 2 7.0 0.5 0.0 mul x0, x0, x0
+# CHECK-NEXT: 1. 2 10.0 0.0 0.0 madd x0, x1, x2, x0
+# CHECK-NEXT: 2. 2 13.0 0.0 0.0 madd x0, x1, x2, x0
+# CHECK-NEXT: 3. 2 16.0 0.0 0.0 madd x0, x0, x0, x0
+# CHECK-NEXT: 2 11.5 0.1 0.0 <total>
+
+# CHECK: [1] Code Region - smaddl
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 400
+# CHECK-NEXT: Total Cycles: 1203
+# CHECK-NEXT: Total uOps: 400
+
+# CHECK: Dispatch Width: 10
+# CHECK-NEXT: uOps Per Cycle: 0.33
+# CHECK-NEXT: IPC: 0.33
+# CHECK-NEXT: Block RThroughput: 1.0
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 0123456789
+# CHECK-NEXT: Index 0123456789 0123456
+
+# CHECK: [0,0] DeeeER . . . .. mul x0, x0, x0
+# CHECK-NEXT: [0,1] D===eeeER . . . .. smaddl x0, w1, w2, x0
+# CHECK-NEXT: [0,2] D======eeeER . . .. smaddl x0, w1, w2, x0
+# CHECK-NEXT: [0,3] D=========eeeER. . .. smaddl x0, w0, w0, x0
+# CHECK-NEXT: [1,0] D============eeeER . .. mul x0, x0, x0
+# CHECK-NEXT: [1,1] D===============eeeER .. smaddl x0, w1, w2, x0
+# CHECK-NEXT: [1,2] D==================eeeER .. smaddl x0, w1, w2, x0
+# CHECK-NEXT: [1,3] D=====================eeeER smaddl x0, w0, w0, x0
----------------
Asher8118 wrote:
Same here for multiply accumulate long. Late-forwarding needs to be added to the scheduler model.
https://github.com/llvm/llvm-project/pull/182251
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