[llvm] [AArch64] C1-Ultra Scheduling model (PR #182251)

[Asher Dobrescu via llvm-commits]

https://github.com/Asher8118 requested changes to this pull request.

Hello, I've gone through the tests and have a few comments relating to latency and throughput of instructions. I have written some bullet points to summarise the issues I found. I hope this will make it easier to parse through the comments:

- Check neon instructions that show throughput of 1 in tests. There are currently too many instructions showing throughput 1 which makes me believe something is not right.
- Look at ASIMD store instructions that have varying throughput, but use the same resources. I think there are some that show wrong throughput information.
- Similarly to the neon instructions, there seem to be too many SVE instructions showing throughput 1. For example: all cases of [floating point associative add.](https://github.com/nasherm/llvm-project/blob/0a875d6b1810ebbdaaf60f161b497c5c1aef145a/llvm/test/tools/llvm-mca/AArch64/Cortex/Ultra-sve-instructions.s#L584). The latency is correct, but the throughput is wrong in all cases. For [floating point associative add, F64 ](https://github.com/nasherm/llvm-project/blob/0a875d6b1810ebbdaaf60f161b497c5c1aef145a/llvm/test/tools/llvm-mca/AArch64/Cortex/Ultra-sve-instructions.s#L583)the throughput is not shown as 1, but it is still incorrect.
- There are some late-forwarding instructions that are supported in C1-Ultra that have not been added to the scheduler model and tests.

https://github.com/llvm/llvm-project/pull/182251