[llvm] [AArch64] C1-Ultra Scheduling model (PR #182251)

[Asher Dobrescu via llvm-commits]

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@@ -0,0 +1,3167 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=aarch64 -mcpu=c1-ultra -mattr=+aes -instruction-tables < %p/../Inputs/neon-instructions.s | FileCheck %s
+
+# CHECK:      Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
+# CHECK-NEXT:  1      2     0.17                        abs	d29, d24
+# CHECK-NEXT:  1      2     0.17                        abs	v0.16b, v0.16b
+# CHECK-NEXT:  1      2     0.17                        abs	v0.2d, v0.2d
+# CHECK-NEXT:  1      2     0.17                        abs	v0.2s, v0.2s
+# CHECK-NEXT:  1      2     0.17                        abs	v0.4h, v0.4h
+# CHECK-NEXT:  1      2     0.17                        abs	v0.4s, v0.4s
+# CHECK-NEXT:  1      2     0.17                        abs	v0.8b, v0.8b
+# CHECK-NEXT:  1      2     0.17                        abs	v0.8h, v0.8h
+# CHECK-NEXT:  1      2     0.17                        add	d17, d31, d29
+# CHECK-NEXT:  1      2     0.17                        add	v0.8b, v0.8b, v0.8b
+# CHECK-NEXT:  1      2     0.17                        addhn	v0.2s, v0.2d, v0.2d
+# CHECK-NEXT:  1      2     0.17                        addhn	v0.4h, v0.4s, v0.4s
+# CHECK-NEXT:  1      2     0.17                        addhn	v0.8b, v0.8h, v0.8h
+# CHECK-NEXT:  1      2     0.17                        addhn2	v0.16b, v0.8h, v0.8h
+# CHECK-NEXT:  1      2     0.17                        addhn2	v0.4s, v0.2d, v0.2d
+# CHECK-NEXT:  1      2     0.17                        addhn2	v0.8h, v0.4s, v0.4s
+# CHECK-NEXT:  1      2     0.17                        addp	v7.2s, v1.2s, v2.2s
+# CHECK-NEXT:  1      2     0.17                        addp	v0.2d, v0.2d, v0.2d
+# CHECK-NEXT:  1      2     0.17                        addp	v0.8b, v0.8b, v0.8b
+# CHECK-NEXT:  1      2     0.17                        addp	d1, v14.2d
+# CHECK-NEXT:  1      2     1.00                        addv	s0, v0.4s
+# CHECK-NEXT:  1      2     1.00                        addv	h0, v0.4h
+# CHECK-NEXT:  1      4     1.00                        addv	h0, v0.8h
+# CHECK-NEXT:  1      4     1.00                        addv	b0, v0.8b
+# CHECK-NEXT:  1      4     1.00                        addv	b0, v0.16b
+# CHECK-NEXT:  1      2     1.00                        aesd	v0.16b, v0.16b
+# CHECK-NEXT:  1      2     1.00                        aese	v0.16b, v0.16b
+# CHECK-NEXT:  1      2     1.00                        aesimc	v0.16b, v0.16b
+# CHECK-NEXT:  1      2     1.00                        aesmc	v0.16b, v0.16b
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Asher8118 wrote:

I don't think the throughput here is right, it shows as 4 (except for ASIMD arith, reduce 16b where throughput should be 2) in the SWOG.

https://github.com/llvm/llvm-project/pull/182251