[llvm] [RISCV][P-ext] Support vector ISD::ABS using PDIF instructions. (PR #184822)
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Thu Mar 5 08:32:29 PST 2026
https://github.com/topperc created https://github.com/llvm/llvm-project/pull/184822
None
>From e77c22724358ec61d3f665eb43af5a924185f1de Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Thu, 5 Mar 2026 08:22:48 -0800
Subject: [PATCH 1/2] Pre-commit test
---
llvm/test/CodeGen/RISCV/rvp-ext-rv32.ll | 30 ++++++++++++++---
llvm/test/CodeGen/RISCV/rvp-ext-rv64.ll | 45 +++++++++++++++++++++----
2 files changed, 65 insertions(+), 10 deletions(-)
diff --git a/llvm/test/CodeGen/RISCV/rvp-ext-rv32.ll b/llvm/test/CodeGen/RISCV/rvp-ext-rv32.ll
index ea042c51babfa..ccd5e7ae778a0 100644
--- a/llvm/test/CodeGen/RISCV/rvp-ext-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvp-ext-rv32.ll
@@ -310,6 +310,28 @@ define <4 x i8> @test_paaddu_b(<4 x i8> %a, <4 x i8> %b) {
ret <4 x i8> %res
}
+define <2 x i16> @test_pabs_h(<2 x i16> %a) {
+; CHECK-LABEL: test_pabs_h:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pli.h a1, 0
+; CHECK-NEXT: psub.h a1, a1, a0
+; CHECK-NEXT: pmax.h a0, a0, a1
+; CHECK-NEXT: ret
+ %res = call <2 x i16> @llvm.abs.v2i16(<2 x i16> %a, i1 0)
+ ret <2 x i16> %res
+}
+
+define <4 x i8> @test_pabs_b(<4 x i8> %a) {
+; CHECK-LABEL: test_pabs_b:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pli.b a1, 0
+; CHECK-NEXT: psub.b a1, a1, a0
+; CHECK-NEXT: pmax.b a0, a0, a1
+; CHECK-NEXT: ret
+ %res = call <4 x i8> @llvm.abs.v4i8(<4 x i8> %a, i1 0)
+ ret <4 x i8> %res
+}
+
; Test absolute difference signed for v2i16
define <2 x i16> @test_pdif_h(<2 x i16> %a, <2 x i16> %b) {
; CHECK-LABEL: test_pdif_h:
@@ -1699,10 +1721,10 @@ define <2 x i16> @test_select_v2i16(i1 %cond, <2 x i16> %a, <2 x i16> %b) {
; CHECK: # %bb.0:
; CHECK-NEXT: andi a3, a0, 1
; CHECK-NEXT: mv a0, a1
-; CHECK-NEXT: bnez a3, .LBB119_2
+; CHECK-NEXT: bnez a3, .LBB121_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a0, a2
-; CHECK-NEXT: .LBB119_2:
+; CHECK-NEXT: .LBB121_2:
; CHECK-NEXT: ret
%res = select i1 %cond, <2 x i16> %a, <2 x i16> %b
ret <2 x i16> %res
@@ -1713,10 +1735,10 @@ define <4 x i8> @test_select_v4i8(i1 %cond, <4 x i8> %a, <4 x i8> %b) {
; CHECK: # %bb.0:
; CHECK-NEXT: andi a3, a0, 1
; CHECK-NEXT: mv a0, a1
-; CHECK-NEXT: bnez a3, .LBB120_2
+; CHECK-NEXT: bnez a3, .LBB122_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a0, a2
-; CHECK-NEXT: .LBB120_2:
+; CHECK-NEXT: .LBB122_2:
; CHECK-NEXT: ret
%res = select i1 %cond, <4 x i8> %a, <4 x i8> %b
ret <4 x i8> %res
diff --git a/llvm/test/CodeGen/RISCV/rvp-ext-rv64.ll b/llvm/test/CodeGen/RISCV/rvp-ext-rv64.ll
index 038b6384a9a43..420eeb2f2ea2e 100644
--- a/llvm/test/CodeGen/RISCV/rvp-ext-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvp-ext-rv64.ll
@@ -374,6 +374,39 @@ define <8 x i8> @test_paaddu_b(<8 x i8> %a, <8 x i8> %b) {
ret <8 x i8> %res
}
+define <2 x i32> @test_pabs_w(<2 x i32> %a) {
+; CHECK-LABEL: test_pabs_w:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pli.w a1, 0
+; CHECK-NEXT: psub.w a1, a1, a0
+; CHECK-NEXT: pmax.w a0, a0, a1
+; CHECK-NEXT: ret
+ %res = call <2 x i32> @llvm.abs.v2i32(<2 x i32> %a, i1 0)
+ ret <2 x i32> %res
+}
+
+define <4 x i16> @test_pabs_h(<4 x i16> %a) {
+; CHECK-LABEL: test_pabs_h:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pli.h a1, 0
+; CHECK-NEXT: psub.h a1, a1, a0
+; CHECK-NEXT: pmax.h a0, a0, a1
+; CHECK-NEXT: ret
+ %res = call <4 x i16> @llvm.abs.v4i16(<4 x i16> %a, i1 0)
+ ret <4 x i16> %res
+}
+
+define <8 x i8> @test_pabs_b(<8 x i8> %a) {
+; CHECK-LABEL: test_pabs_b:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pli.b a1, 0
+; CHECK-NEXT: psub.b a1, a1, a0
+; CHECK-NEXT: pmax.b a0, a0, a1
+; CHECK-NEXT: ret
+ %res = call <8 x i8> @llvm.abs.v8i8(<8 x i8> %a, i1 0)
+ ret <8 x i8> %res
+}
+
; Test absolute difference signed for v2i32
; abds pattern: sub(smax(a,b), smin(a,b))
define <2 x i32> @test_pdif_w(<2 x i32> %a, <2 x i32> %b) {
@@ -2035,10 +2068,10 @@ define <4 x i16> @test_select_v4i16(i1 %cond, <4 x i16> %a, <4 x i16> %b) {
; CHECK: # %bb.0:
; CHECK-NEXT: andi a3, a0, 1
; CHECK-NEXT: mv a0, a1
-; CHECK-NEXT: bnez a3, .LBB163_2
+; CHECK-NEXT: bnez a3, .LBB166_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a0, a2
-; CHECK-NEXT: .LBB163_2:
+; CHECK-NEXT: .LBB166_2:
; CHECK-NEXT: ret
%res = select i1 %cond, <4 x i16> %a, <4 x i16> %b
ret <4 x i16> %res
@@ -2049,10 +2082,10 @@ define <8 x i8> @test_select_v8i8(i1 %cond, <8 x i8> %a, <8 x i8> %b) {
; CHECK: # %bb.0:
; CHECK-NEXT: andi a3, a0, 1
; CHECK-NEXT: mv a0, a1
-; CHECK-NEXT: bnez a3, .LBB164_2
+; CHECK-NEXT: bnez a3, .LBB167_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a0, a2
-; CHECK-NEXT: .LBB164_2:
+; CHECK-NEXT: .LBB167_2:
; CHECK-NEXT: ret
%res = select i1 %cond, <8 x i8> %a, <8 x i8> %b
ret <8 x i8> %res
@@ -2063,10 +2096,10 @@ define <2 x i32> @test_select_v2i32(i1 %cond, <2 x i32> %a, <2 x i32> %b) {
; CHECK: # %bb.0:
; CHECK-NEXT: andi a3, a0, 1
; CHECK-NEXT: mv a0, a1
-; CHECK-NEXT: bnez a3, .LBB165_2
+; CHECK-NEXT: bnez a3, .LBB168_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a0, a2
-; CHECK-NEXT: .LBB165_2:
+; CHECK-NEXT: .LBB168_2:
; CHECK-NEXT: ret
%res = select i1 %cond, <2 x i32> %a, <2 x i32> %b
ret <2 x i32> %res
>From b9804069fbe6eb7b9a4de08248d55237182ff310 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Thu, 5 Mar 2026 08:30:47 -0800
Subject: [PATCH 2/2] [RISCV][P-ext] Support vector ISD::ABS using PDIF
instructions.
---
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 2 +-
llvm/lib/Target/RISCV/RISCVInstrInfoP.td | 2 ++
llvm/test/CodeGen/RISCV/rvp-ext-rv32.ll | 8 ++------
llvm/test/CodeGen/RISCV/rvp-ext-rv64.ll | 8 ++------
4 files changed, 7 insertions(+), 13 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 74b70b6642cd9..29eff7a9a560e 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -577,7 +577,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
setOperationAction({ISD::AVGFLOORS, ISD::AVGFLOORU}, VTs, Legal);
for (MVT VT : VTs)
if (VT != MVT::v2i32)
- setOperationAction({ISD::ABDS, ISD::ABDU}, VT, Legal);
+ setOperationAction({ISD::ABS, ISD::ABDS, ISD::ABDU}, VT, Legal);
setOperationAction(ISD::SPLAT_VECTOR, VTs, Legal);
setOperationAction(ISD::BUILD_VECTOR, VTs, Legal);
setOperationAction(ISD::SCALAR_TO_VECTOR, VTs, Legal);
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoP.td b/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
index f82ff91eecdb3..86bcb0b1ff3c3 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
@@ -1748,10 +1748,12 @@ let Predicates = [HasStdExtP] in {
def: Pat<(XLenVecI16VT (riscv_asubu GPR:$rs1, GPR:$rs2)), (PASUBU_H GPR:$rs1, GPR:$rs2)>;
// 8-bit absolute difference patterns
+ def: Pat<(XLenVecI8VT (abs GPR:$rs1)), (PABD_B GPR:$rs1, (XLenVecI8VT X0))>;
def: Pat<(XLenVecI8VT (abds GPR:$rs1, GPR:$rs2)), (PABD_B GPR:$rs1, GPR:$rs2)>;
def: Pat<(XLenVecI8VT (abdu GPR:$rs1, GPR:$rs2)), (PABDU_B GPR:$rs1, GPR:$rs2)>;
// 16-bit absolute difference patterns
+ def: Pat<(XLenVecI16VT (abs GPR:$rs1)), (PABD_H GPR:$rs1, (XLenVecI16VT X0))>;
def: Pat<(XLenVecI16VT (abds GPR:$rs1, GPR:$rs2)), (PABD_H GPR:$rs1, GPR:$rs2)>;
def: Pat<(XLenVecI16VT (abdu GPR:$rs1, GPR:$rs2)), (PABDU_H GPR:$rs1, GPR:$rs2)>;
diff --git a/llvm/test/CodeGen/RISCV/rvp-ext-rv32.ll b/llvm/test/CodeGen/RISCV/rvp-ext-rv32.ll
index ccd5e7ae778a0..4412e55174af9 100644
--- a/llvm/test/CodeGen/RISCV/rvp-ext-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvp-ext-rv32.ll
@@ -313,9 +313,7 @@ define <4 x i8> @test_paaddu_b(<4 x i8> %a, <4 x i8> %b) {
define <2 x i16> @test_pabs_h(<2 x i16> %a) {
; CHECK-LABEL: test_pabs_h:
; CHECK: # %bb.0:
-; CHECK-NEXT: pli.h a1, 0
-; CHECK-NEXT: psub.h a1, a1, a0
-; CHECK-NEXT: pmax.h a0, a0, a1
+; CHECK-NEXT: pabd.h a0, a0, zero
; CHECK-NEXT: ret
%res = call <2 x i16> @llvm.abs.v2i16(<2 x i16> %a, i1 0)
ret <2 x i16> %res
@@ -324,9 +322,7 @@ define <2 x i16> @test_pabs_h(<2 x i16> %a) {
define <4 x i8> @test_pabs_b(<4 x i8> %a) {
; CHECK-LABEL: test_pabs_b:
; CHECK: # %bb.0:
-; CHECK-NEXT: pli.b a1, 0
-; CHECK-NEXT: psub.b a1, a1, a0
-; CHECK-NEXT: pmax.b a0, a0, a1
+; CHECK-NEXT: pabd.b a0, a0, zero
; CHECK-NEXT: ret
%res = call <4 x i8> @llvm.abs.v4i8(<4 x i8> %a, i1 0)
ret <4 x i8> %res
diff --git a/llvm/test/CodeGen/RISCV/rvp-ext-rv64.ll b/llvm/test/CodeGen/RISCV/rvp-ext-rv64.ll
index 420eeb2f2ea2e..fa2e7ebeded28 100644
--- a/llvm/test/CodeGen/RISCV/rvp-ext-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvp-ext-rv64.ll
@@ -388,9 +388,7 @@ define <2 x i32> @test_pabs_w(<2 x i32> %a) {
define <4 x i16> @test_pabs_h(<4 x i16> %a) {
; CHECK-LABEL: test_pabs_h:
; CHECK: # %bb.0:
-; CHECK-NEXT: pli.h a1, 0
-; CHECK-NEXT: psub.h a1, a1, a0
-; CHECK-NEXT: pmax.h a0, a0, a1
+; CHECK-NEXT: pabd.h a0, a0, zero
; CHECK-NEXT: ret
%res = call <4 x i16> @llvm.abs.v4i16(<4 x i16> %a, i1 0)
ret <4 x i16> %res
@@ -399,9 +397,7 @@ define <4 x i16> @test_pabs_h(<4 x i16> %a) {
define <8 x i8> @test_pabs_b(<8 x i8> %a) {
; CHECK-LABEL: test_pabs_b:
; CHECK: # %bb.0:
-; CHECK-NEXT: pli.b a1, 0
-; CHECK-NEXT: psub.b a1, a1, a0
-; CHECK-NEXT: pmax.b a0, a0, a1
+; CHECK-NEXT: pabd.b a0, a0, zero
; CHECK-NEXT: ret
%res = call <8 x i8> @llvm.abs.v8i8(<8 x i8> %a, i1 0)
ret <8 x i8> %res
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