[llvm] [AMDGPU] Register allocation anti-hints to reduce MFMA hazard NOPs (PR #156943)

[via llvm-commits]

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@@ -243,8 +252,136 @@ bool GCNPreRAOptimizationsImpl::run(MachineFunction &MF) {
   TII = ST.getInstrInfo();
   MRI = &MF.getRegInfo();
   TRI = ST.getRegisterInfo();
+  SchedModel.init(&ST);
 
   bool Changed = false;
+  // Add RA anti-hints to reduce MFMA hazard NOPs
+  if (EnableAntiHintsForMFMARegs && ST.hasMAIInsts()) {
+    // Max lookback window for RAW or WAW hazard (in instructions)
+    constexpr unsigned MaxLookbackWindow = 19;
+
+    // Per-MFMA tracking to determine anti-hint eligibility for subsequent
+    // instructions within the max lookback window.
+    struct MFMAInfo {
+      SmallVector<Register, 4> Regs;
+      unsigned InstrCount;
+      unsigned MFMALatency;
+      unsigned CumulativeLatencySinceThisMFMA;
+    };
+
+    for (const MachineBasicBlock &MBB : MF) {
+      SmallVector<MFMAInfo, 16> RecentMFMAs;
+      unsigned InstrCount = 0;
+
+      for (const MachineInstr &MI : MBB) {
+        if (MI.isDebugInstr())
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LU-JOHN wrote:

isMetaInstruction would avoid more instructions that don't take cycles.



https://github.com/llvm/llvm-project/pull/156943