[llvm] [AArch64] Add extra sched predicates (PR #184801)

[Nashe Mncube via llvm-commits]

https://github.com/nasherm created https://github.com/llvm/llvm-project/pull/184801

Add predicates for the following checks
 - check that destination and source Z registers are equivalent
 - check that for FP instructions are Q form


>From c529198eabe85e3df06534d12d2910f00207a015 Mon Sep 17 00:00:00 2001
From: nasmnc01 <nashe.mncube at arm.com>
Date: Thu, 5 Mar 2026 14:18:33 +0000
Subject: [PATCH] [AArch64] Add extra sched predicates

Add predicates for the following checks
 - check that destination and source Z registers are equivalent
 - check that for FP instructions are Q form

Change-Id: I6296432e19180e6ec60499c9ab639eb45a5e9aac
---
 .../Target/AArch64/AArch64SchedPredicates.td  | 27 +++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/llvm/lib/Target/AArch64/AArch64SchedPredicates.td b/llvm/lib/Target/AArch64/AArch64SchedPredicates.td
index 854d3ce564831..3759d56b1637a 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedPredicates.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedPredicates.td
@@ -343,3 +343,30 @@ def IsZeroFPIdiomPred : MCSchedPredicate<IsZeroFPIdiomFn>;
 def IsRORImmIdiomPred : MCSchedPredicate< // EXTR Rd, Rs, Rs, #Imm
                           CheckAll<[CheckOpcode<[EXTRWrri, EXTRXrri]>,
                                     CheckSameRegOperand<1, 2>]>>;
+def CheckIsZRegOp0 : CheckAll<[
+  CheckIsRegOperand<0>,
+  CheckAny<[
+    CheckRegOperand<0, Z0>,  CheckRegOperand<0, Z1>,  CheckRegOperand<0, Z2>,
+    CheckRegOperand<0, Z3>,  CheckRegOperand<0, Z4>,  CheckRegOperand<0, Z5>,
+    CheckRegOperand<0, Z6>,  CheckRegOperand<0, Z7>,  CheckRegOperand<0, Z8>,
+    CheckRegOperand<0, Z9>,  CheckRegOperand<0, Z10>, CheckRegOperand<0, Z11>,
+    CheckRegOperand<0, Z12>, CheckRegOperand<0, Z13>, CheckRegOperand<0, Z14>,
+    CheckRegOperand<0, Z15>, CheckRegOperand<0, Z16>, CheckRegOperand<0, Z17>,
+    CheckRegOperand<0, Z18>, CheckRegOperand<0, Z19>, CheckRegOperand<0, Z20>,
+    CheckRegOperand<0, Z21>, CheckRegOperand<0, Z22>, CheckRegOperand<0, Z23>,
+    CheckRegOperand<0, Z24>, CheckRegOperand<0, Z25>, CheckRegOperand<0, Z26>,
+    CheckRegOperand<0, Z27>, CheckRegOperand<0, Z28>, CheckRegOperand<0, Z29>,
+    CheckRegOperand<0, Z30>, CheckRegOperand<0, Z31>
+  ]>
+]>;
+
+// Check if destination and source are the same Z register (Zn == Zm)
+def SameZRegDstSrcPred : MCSchedPredicate<
+  CheckAll<[CheckSameRegOperand<0, 1>, CheckIsZRegOp0]>
+>;
+
+// Identify LDR/STR Q-form scaled (and potentially extended) FP instructions
+def FPIsQForm : MCSchedPredicate<
+                       CheckAll<[
+                         CheckAny<[CheckQForm]>,
+                         CheckImmOperand<4, 1>]>>;