[llvm] [RISCV] Add contraints for SpacemiT X60 AI VDot Insts (PR #174364)

[via llvm-commits]

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@@ -3842,25 +3852,35 @@ bool RISCVAsmParser::validateInstruction(MCInst &Inst,
   assert(ParsedOp->getReg() == DestReg && "Can't find parsed dest operand");
   SMLoc Loc = ParsedOp->getStartLoc();
 
+  unsigned Lmul = getLMULFromVectorRegister(DestReg);
+  unsigned DestEncoding =
+      getContext().getRegisterInfo()->getEncodingValue(DestReg);
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LiqinWeng wrote:

ping~

https://github.com/llvm/llvm-project/pull/174364