[llvm] [RISCV] Implement `isLoadFromStackSlotPostFE` and ... (PR #184673)

[Sam Elliott via llvm-commits]

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@@ -182,6 +182,27 @@ Register RISCVInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
   return 0;
 }
 
+Register RISCVInstrInfo::isLoadFromStackSlotPostFE(const MachineInstr &MI,
+                                                   int &FrameIndex) const {
+  if (!MI.mayLoad())
+    return Register();
+
+  if (Register Reg = isLoadFromStackSlot(MI, FrameIndex))
+    return Reg;
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lenary wrote:

So I do see the other backends are calling this too, but I'm not sure it's "helpful" - if this callback is "post frame elimination" as the name implies, then you shouldn't have any frame indexes, so `isLoadFromStackSlot` won't be helpful.

Do you have cases where this is helpful?



https://github.com/llvm/llvm-project/pull/184673