[llvm] AMDGPU/GlobalISel: RegBankLegalize rules for amdgcn_exp/exp_row (PR #181956)

[Petar Avramovic via llvm-commits]

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@@ -221,6 +221,9 @@ enum RegBankLLTMappingApplyID {
   Sgpr32_WF,
   SgprV4S32_WF,
 
+  // Src only modifiers: readfirstlane to M0 if divergent (not waterfall)
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petar-avramovic wrote:

Comment is kind of not correct, need to explain it better
M0 is not a thing this early but sure, SgprB32_M0 operands will be copied to m0 and machine instruction will read from it
but it will not readfirstlane to m0, but to random sgpr, then move that sgpr to m0

https://github.com/llvm/llvm-project/pull/181956