[llvm] [RISCV] Lower i8/i16/i32 scalable vector ISD::CLMUL/CLMULH with Zvbc32e. (PR #184465)

Craig Topper via llvm-commits llvm-commits at lists.llvm.org
Wed Mar 4 08:29:16 PST 2026

Previous message: [llvm] [RISCV] Lower i8/i16/i32 scalable vector ISD::CLMUL/CLMULH with Zvbc32e. (PR #184465)
Next message: [llvm] [LoopUnroll][NFC] Record conditional latch info (PR #182403)
Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

https://github.com/topperc closed https://github.com/llvm/llvm-project/pull/184465

Previous message: [llvm] [RISCV] Lower i8/i16/i32 scalable vector ISD::CLMUL/CLMULH with Zvbc32e. (PR #184465)
Next message: [llvm] [LoopUnroll][NFC] Record conditional latch info (PR #182403)
Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

More information about the llvm-commits mailing list