[clang] [llvm] [X86] Reduce -ffixed-r compile-time overhead (PR #184606)

[via llvm-commits]

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@@ -67,7 +67,7 @@ class X86Subtarget final : public X86GenSubtargetInfo {
   bool ATTRIBUTE = DEFAULT;
 #include "X86GenSubtargetInfo.inc"
   /// ReservedRReg R#i is not available as a general purpose register.
-  BitVector ReservedRReg;
+  std::bitset<X86::NUM_TARGET_REGS> ReservedRReg;
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zhouguangyuan0718 wrote:

`ReservedRReg` will be accessed directly with the register index, which mean the index in it should match the definition of register number, and the register number of r8-r31 is not 8~31, so we need the size of total registers. 
RISCV also define it like this: https://github.com/llvm/llvm-project/blob/b68307569bb955fb2f613bd239ad7a92e805035f/llvm/lib/Target/RISCV/RISCVSubtarget.h#L112

https://github.com/llvm/llvm-project/pull/184606