[llvm] [AMDGPU][GlobalISel] Fix VCC s1 phi instruction selection failure (PR #184632)
Arseniy Obolenskiy via llvm-commits
llvm-commits at lists.llvm.org
Wed Mar 4 07:39:19 PST 2026
https://github.com/aobolensk created https://github.com/llvm/llvm-project/pull/184632
VCC s1 phis cannot be ISel'd (`SIInstrInfo::selectPHI` returns false for S1 types), and the VCC register class only supports s1 type. This caused the following instruction selection failure:
```
cannot select: %N:sreg_64_xexec(s1) = G_PHI %M:vcc(s1), ...
```
Notes:
- The existing regbankselect-phi-s1.mir test only ran `-run-pass=regbankselect`, so VCC s1 phis were not verified by ISel, so the changes had to be applied for the existing regbank tests as well.
- Extra semicolon changes were generated by `utils/update_*_test_checks.py` scripts
>From 4cad1783ef1b8f5703cca5d78e8313896ddca8e7 Mon Sep 17 00:00:00 2001
From: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: Wed, 4 Mar 2026 16:24:43 +0100
Subject: [PATCH] [AMDGPU][GlobalISel] Fix VCC S1 phi instruction selection
failure
VCC S1 phis cannot be ISel'd because SIInstrInfo::selectPHI returns false for S1 types, and the VCC register class only supports S1. This caused the following instruction selection failure:
```
cannot select: %N:sreg_64_xexec(s1) = G_PHI %M:vcc(s1), ...
```
The existing regbankselect-phi-s1.mir test only ran `-run-pass=regbankselect`, so VCC S1 phis were not verified by ISel, so the changes were applied to the existing tests as well
---
.../Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 29 +++
.../GlobalISel/regbankselect-phi-s1.mir | 194 +++++++++++------
.../AMDGPU/GlobalISel/regbankselect-phi.mir | 186 +++++++++++-----
.../CodeGen/AMDGPU/GlobalISel/vcc-s1-phi.ll | 198 ++++++++++++++++++
4 files changed, 489 insertions(+), 118 deletions(-)
create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/vcc-s1-phi.ll
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
index 7e047278fe78f..112aebbbba55c 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
@@ -2265,6 +2265,29 @@ void AMDGPURegisterBankInfo::applyMappingImpl(
// Phi handling is strange and only considers the bank of the destination.
substituteSimpleCopyRegs(OpdMapper, 0);
+ // Convert VCC S1 inputs to SGPR before widening to avoid incorrect
+ // VCC->VGPR conversion in ApplyRegBankMapping.
+ if (DstBank == &AMDGPU::SGPRRegBank) {
+ for (unsigned I = 1, E = MI.getNumOperands(); I != E; I += 2) {
+ Register SrcReg = MI.getOperand(I).getReg();
+ const RegisterBank *SrcBank = getRegBank(SrcReg, MRI, *TRI);
+
+ if (SrcBank == &AMDGPU::VCCRegBank) {
+ MachineBasicBlock *SrcMBB = MI.getOperand(I + 1).getMBB();
+ B.setInsertPt(*SrcMBB, SrcMBB->getFirstTerminator());
+
+ auto CopySccVcc = B.buildInstr(AMDGPU::G_AMDGPU_COPY_SCC_VCC, {S32},
+ {SrcReg});
+ MRI.setRegBank(CopySccVcc.getReg(0), AMDGPU::SGPRRegBank);
+
+ // Truncate to S1 for phi input (widened to S32 later with SGPR bank)
+ auto Trunc = B.buildTrunc(LLT::scalar(1), CopySccVcc);
+ MRI.setRegBank(Trunc.getReg(0), AMDGPU::SGPRRegBank);
+ MI.getOperand(I).setReg(Trunc.getReg(0));
+ }
+ }
+ }
+
// Promote SGPR/VGPR booleans to s32
ApplyRegBankMapping ApplyBank(B, *this, MRI, DstBank);
B.setInsertPt(B.getMBB(), MI);
@@ -3944,6 +3967,12 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
unsigned Size = MRI.getType(DstReg).getSizeInBits();
+ // VCC S1 phis cannot be instruction-selected. Use SGPR bank instead,
+ // widened to S32 in applyMapping with VCC inputs converted via
+ // G_AMDGPU_COPY_SCC_VCC.
+ if (Size == 1 && ResultBank == AMDGPU::VCCRegBankID)
+ ResultBank = AMDGPU::SGPRRegBankID;
+
const ValueMapping &ValMap =
getValueMapping(0, Size, getRegBank(ResultBank));
return getInstructionMapping(
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi-s1.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi-s1.mir
index 39e421c1b8f94..1c9f0e56ac080 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi-s1.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi-s1.mir
@@ -40,6 +40,7 @@ body: |
; FAST-NEXT: [[ZEXT1:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC3]](s1)
; FAST-NEXT: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ZEXT1]](s32), [[C]], [[COPY]]
; FAST-NEXT: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32)
+ ;
; GREEDY-LABEL: name: phi_s1_scc_scc_sbranch
; GREEDY: bb.0:
; GREEDY-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
@@ -152,6 +153,7 @@ body: |
; FAST-NEXT: [[ZEXT2:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC5]](s1)
; FAST-NEXT: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ZEXT2]](s32), [[COPY]], [[COPY1]]
; FAST-NEXT: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32)
+ ;
; GREEDY-LABEL: name: phi_s1_scc_scc_scc_sbranch
; GREEDY: bb.0:
; GREEDY-NEXT: successors: %bb.1(0x40000000), %bb.3(0x40000000)
@@ -258,23 +260,27 @@ body: |
; FAST-NEXT: [[ICMP1:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
; FAST-NEXT: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP1]](s32)
; FAST-NEXT: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC1]](s1)
- ; FAST-NEXT: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
+ ; FAST-NEXT: [[ANYEXT:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[TRUNC]](s1)
; FAST-NEXT: G_BRCOND [[ZEXT]](s32), %bb.1
; FAST-NEXT: G_BR %bb.2
; FAST-NEXT: {{ $}}
; FAST-NEXT: bb.1:
; FAST-NEXT: successors: %bb.2(0x80000000)
; FAST-NEXT: {{ $}}
- ; FAST-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
- ; FAST-NEXT: [[ICMP2:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY4]]
+ ; FAST-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
+ ; FAST-NEXT: [[ICMP2:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
+ ; FAST-NEXT: [[AMDGPU_COPY_SCC_VCC:%[0-9]+]]:sgpr(s32) = G_AMDGPU_COPY_SCC_VCC [[ICMP2]](s1)
+ ; FAST-NEXT: [[TRUNC2:%[0-9]+]]:sgpr(s1) = G_TRUNC [[AMDGPU_COPY_SCC_VCC]](s32)
+ ; FAST-NEXT: [[ANYEXT1:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[TRUNC2]](s1)
; FAST-NEXT: G_BR %bb.2
; FAST-NEXT: {{ $}}
; FAST-NEXT: bb.2:
- ; FAST-NEXT: [[PHI:%[0-9]+]]:vcc(s1) = G_PHI [[COPY3]](s1), %bb.0, [[ICMP2]](s1), %bb.1
- ; FAST-NEXT: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
- ; FAST-NEXT: [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
- ; FAST-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[PHI]](s1), [[COPY5]], [[COPY6]]
+ ; FAST-NEXT: [[PHI:%[0-9]+]]:sgpr(s32) = G_PHI [[ANYEXT]](s32), %bb.0, [[ANYEXT1]](s32), %bb.1
+ ; FAST-NEXT: [[TRUNC3:%[0-9]+]]:sgpr(s1) = G_TRUNC [[PHI]](s32)
+ ; FAST-NEXT: [[ZEXT1:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC3]](s1)
+ ; FAST-NEXT: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ZEXT1]](s32), [[C]], [[COPY]]
; FAST-NEXT: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32)
+ ;
; GREEDY-LABEL: name: phi_s1_scc_vcc_sbranch
; GREEDY: bb.0:
; GREEDY-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
@@ -289,22 +295,25 @@ body: |
; GREEDY-NEXT: [[ICMP1:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
; GREEDY-NEXT: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP1]](s32)
; GREEDY-NEXT: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC1]](s1)
- ; GREEDY-NEXT: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
+ ; GREEDY-NEXT: [[ANYEXT:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[TRUNC]](s1)
; GREEDY-NEXT: G_BRCOND [[ZEXT]](s32), %bb.1
; GREEDY-NEXT: G_BR %bb.2
; GREEDY-NEXT: {{ $}}
; GREEDY-NEXT: bb.1:
; GREEDY-NEXT: successors: %bb.2(0x80000000)
; GREEDY-NEXT: {{ $}}
- ; GREEDY-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
- ; GREEDY-NEXT: [[ICMP2:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY4]]
+ ; GREEDY-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
+ ; GREEDY-NEXT: [[ICMP2:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
+ ; GREEDY-NEXT: [[AMDGPU_COPY_SCC_VCC:%[0-9]+]]:sgpr(s32) = G_AMDGPU_COPY_SCC_VCC [[ICMP2]](s1)
+ ; GREEDY-NEXT: [[TRUNC2:%[0-9]+]]:sgpr(s1) = G_TRUNC [[AMDGPU_COPY_SCC_VCC]](s32)
+ ; GREEDY-NEXT: [[ANYEXT1:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[TRUNC2]](s1)
; GREEDY-NEXT: G_BR %bb.2
; GREEDY-NEXT: {{ $}}
; GREEDY-NEXT: bb.2:
- ; GREEDY-NEXT: [[PHI:%[0-9]+]]:vcc(s1) = G_PHI [[COPY3]](s1), %bb.0, [[ICMP2]](s1), %bb.1
- ; GREEDY-NEXT: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
- ; GREEDY-NEXT: [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
- ; GREEDY-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[PHI]](s1), [[COPY5]], [[COPY6]]
+ ; GREEDY-NEXT: [[PHI:%[0-9]+]]:sgpr(s32) = G_PHI [[ANYEXT]](s32), %bb.0, [[ANYEXT1]](s32), %bb.1
+ ; GREEDY-NEXT: [[TRUNC3:%[0-9]+]]:sgpr(s1) = G_TRUNC [[PHI]](s32)
+ ; GREEDY-NEXT: [[ZEXT1:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC3]](s1)
+ ; GREEDY-NEXT: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ZEXT1]](s32), [[C]], [[COPY]]
; GREEDY-NEXT: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32)
bb.0:
successors: %bb.1, %bb.2
@@ -352,6 +361,9 @@ body: |
; FAST-NEXT: [[ICMP1:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
; FAST-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP1]](s32)
; FAST-NEXT: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1)
+ ; FAST-NEXT: [[AMDGPU_COPY_SCC_VCC:%[0-9]+]]:sgpr(s32) = G_AMDGPU_COPY_SCC_VCC [[ICMP]](s1)
+ ; FAST-NEXT: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[AMDGPU_COPY_SCC_VCC]](s32)
+ ; FAST-NEXT: [[ANYEXT:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[TRUNC1]](s1)
; FAST-NEXT: G_BRCOND [[ZEXT]](s32), %bb.1
; FAST-NEXT: G_BR %bb.2
; FAST-NEXT: {{ $}}
@@ -359,16 +371,17 @@ body: |
; FAST-NEXT: successors: %bb.2(0x80000000)
; FAST-NEXT: {{ $}}
; FAST-NEXT: [[ICMP2:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]
- ; FAST-NEXT: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP2]](s32)
- ; FAST-NEXT: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[TRUNC1]](s1)
+ ; FAST-NEXT: [[TRUNC2:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP2]](s32)
+ ; FAST-NEXT: [[ANYEXT1:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[TRUNC2]](s1)
; FAST-NEXT: G_BR %bb.2
; FAST-NEXT: {{ $}}
; FAST-NEXT: bb.2:
- ; FAST-NEXT: [[PHI:%[0-9]+]]:vcc(s1) = G_PHI [[ICMP]](s1), %bb.0, [[COPY4]](s1), %bb.1
- ; FAST-NEXT: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
- ; FAST-NEXT: [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
- ; FAST-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[PHI]](s1), [[COPY5]], [[COPY6]]
+ ; FAST-NEXT: [[PHI:%[0-9]+]]:sgpr(s32) = G_PHI [[ANYEXT]](s32), %bb.0, [[ANYEXT1]](s32), %bb.1
+ ; FAST-NEXT: [[TRUNC3:%[0-9]+]]:sgpr(s1) = G_TRUNC [[PHI]](s32)
+ ; FAST-NEXT: [[ZEXT1:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC3]](s1)
+ ; FAST-NEXT: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ZEXT1]](s32), [[C]], [[COPY1]]
; FAST-NEXT: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32)
+ ;
; GREEDY-LABEL: name: phi_s1_vcc_scc_sbranch
; GREEDY: bb.0:
; GREEDY-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
@@ -383,6 +396,9 @@ body: |
; GREEDY-NEXT: [[ICMP1:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
; GREEDY-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP1]](s32)
; GREEDY-NEXT: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1)
+ ; GREEDY-NEXT: [[AMDGPU_COPY_SCC_VCC:%[0-9]+]]:sgpr(s32) = G_AMDGPU_COPY_SCC_VCC [[ICMP]](s1)
+ ; GREEDY-NEXT: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[AMDGPU_COPY_SCC_VCC]](s32)
+ ; GREEDY-NEXT: [[ANYEXT:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[TRUNC1]](s1)
; GREEDY-NEXT: G_BRCOND [[ZEXT]](s32), %bb.1
; GREEDY-NEXT: G_BR %bb.2
; GREEDY-NEXT: {{ $}}
@@ -390,15 +406,15 @@ body: |
; GREEDY-NEXT: successors: %bb.2(0x80000000)
; GREEDY-NEXT: {{ $}}
; GREEDY-NEXT: [[ICMP2:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]
- ; GREEDY-NEXT: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP2]](s32)
- ; GREEDY-NEXT: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[TRUNC1]](s1)
+ ; GREEDY-NEXT: [[TRUNC2:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP2]](s32)
+ ; GREEDY-NEXT: [[ANYEXT1:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[TRUNC2]](s1)
; GREEDY-NEXT: G_BR %bb.2
; GREEDY-NEXT: {{ $}}
; GREEDY-NEXT: bb.2:
- ; GREEDY-NEXT: [[PHI:%[0-9]+]]:vcc(s1) = G_PHI [[ICMP]](s1), %bb.0, [[COPY4]](s1), %bb.1
- ; GREEDY-NEXT: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
- ; GREEDY-NEXT: [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
- ; GREEDY-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[PHI]](s1), [[COPY5]], [[COPY6]]
+ ; GREEDY-NEXT: [[PHI:%[0-9]+]]:sgpr(s32) = G_PHI [[ANYEXT]](s32), %bb.0, [[ANYEXT1]](s32), %bb.1
+ ; GREEDY-NEXT: [[TRUNC3:%[0-9]+]]:sgpr(s1) = G_TRUNC [[PHI]](s32)
+ ; GREEDY-NEXT: [[ZEXT1:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC3]](s1)
+ ; GREEDY-NEXT: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ZEXT1]](s32), [[C]], [[COPY1]]
; GREEDY-NEXT: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32)
bb.0:
successors: %bb.1, %bb.2
@@ -446,6 +462,9 @@ body: |
; FAST-NEXT: [[ICMP1:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
; FAST-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP1]](s32)
; FAST-NEXT: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1)
+ ; FAST-NEXT: [[AMDGPU_COPY_SCC_VCC:%[0-9]+]]:sgpr(s32) = G_AMDGPU_COPY_SCC_VCC [[ICMP]](s1)
+ ; FAST-NEXT: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[AMDGPU_COPY_SCC_VCC]](s32)
+ ; FAST-NEXT: [[ANYEXT:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[TRUNC1]](s1)
; FAST-NEXT: G_BRCOND [[ZEXT]](s32), %bb.1
; FAST-NEXT: G_BR %bb.2
; FAST-NEXT: {{ $}}
@@ -454,13 +473,19 @@ body: |
; FAST-NEXT: {{ $}}
; FAST-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
; FAST-NEXT: [[ICMP2:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY4]]
+ ; FAST-NEXT: [[AMDGPU_COPY_SCC_VCC1:%[0-9]+]]:sgpr(s32) = G_AMDGPU_COPY_SCC_VCC [[ICMP2]](s1)
+ ; FAST-NEXT: [[TRUNC2:%[0-9]+]]:sgpr(s1) = G_TRUNC [[AMDGPU_COPY_SCC_VCC1]](s32)
+ ; FAST-NEXT: [[ANYEXT1:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[TRUNC2]](s1)
; FAST-NEXT: G_BR %bb.2
; FAST-NEXT: {{ $}}
; FAST-NEXT: bb.2:
- ; FAST-NEXT: [[PHI:%[0-9]+]]:vcc(s1) = G_PHI [[ICMP]](s1), %bb.0, [[ICMP2]](s1), %bb.1
- ; FAST-NEXT: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
- ; FAST-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[PHI]](s1), [[COPY5]], [[COPY]]
+ ; FAST-NEXT: [[PHI:%[0-9]+]]:sgpr(s32) = G_PHI [[ANYEXT]](s32), %bb.0, [[ANYEXT1]](s32), %bb.1
+ ; FAST-NEXT: [[TRUNC3:%[0-9]+]]:sgpr(s1) = G_TRUNC [[PHI]](s32)
+ ; FAST-NEXT: [[COPY5:%[0-9]+]]:vcc(s1) = COPY [[TRUNC3]](s1)
+ ; FAST-NEXT: [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
+ ; FAST-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY5]](s1), [[COPY6]], [[COPY]]
; FAST-NEXT: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32)
+ ;
; GREEDY-LABEL: name: phi_s1_vcc_vcc_sbranch
; GREEDY: bb.0:
; GREEDY-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
@@ -475,6 +500,9 @@ body: |
; GREEDY-NEXT: [[ICMP1:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
; GREEDY-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP1]](s32)
; GREEDY-NEXT: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1)
+ ; GREEDY-NEXT: [[AMDGPU_COPY_SCC_VCC:%[0-9]+]]:sgpr(s32) = G_AMDGPU_COPY_SCC_VCC [[ICMP]](s1)
+ ; GREEDY-NEXT: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[AMDGPU_COPY_SCC_VCC]](s32)
+ ; GREEDY-NEXT: [[ANYEXT:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[TRUNC1]](s1)
; GREEDY-NEXT: G_BRCOND [[ZEXT]](s32), %bb.1
; GREEDY-NEXT: G_BR %bb.2
; GREEDY-NEXT: {{ $}}
@@ -483,12 +511,17 @@ body: |
; GREEDY-NEXT: {{ $}}
; GREEDY-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
; GREEDY-NEXT: [[ICMP2:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY4]]
+ ; GREEDY-NEXT: [[AMDGPU_COPY_SCC_VCC1:%[0-9]+]]:sgpr(s32) = G_AMDGPU_COPY_SCC_VCC [[ICMP2]](s1)
+ ; GREEDY-NEXT: [[TRUNC2:%[0-9]+]]:sgpr(s1) = G_TRUNC [[AMDGPU_COPY_SCC_VCC1]](s32)
+ ; GREEDY-NEXT: [[ANYEXT1:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[TRUNC2]](s1)
; GREEDY-NEXT: G_BR %bb.2
; GREEDY-NEXT: {{ $}}
; GREEDY-NEXT: bb.2:
- ; GREEDY-NEXT: [[PHI:%[0-9]+]]:vcc(s1) = G_PHI [[ICMP]](s1), %bb.0, [[ICMP2]](s1), %bb.1
- ; GREEDY-NEXT: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
- ; GREEDY-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[PHI]](s1), [[COPY5]], [[COPY]]
+ ; GREEDY-NEXT: [[PHI:%[0-9]+]]:sgpr(s32) = G_PHI [[ANYEXT]](s32), %bb.0, [[ANYEXT1]](s32), %bb.1
+ ; GREEDY-NEXT: [[TRUNC3:%[0-9]+]]:sgpr(s1) = G_TRUNC [[PHI]](s32)
+ ; GREEDY-NEXT: [[COPY5:%[0-9]+]]:vcc(s1) = COPY [[TRUNC3]](s1)
+ ; GREEDY-NEXT: [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
+ ; GREEDY-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY5]](s1), [[COPY6]], [[COPY]]
; GREEDY-NEXT: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32)
bb.0:
successors: %bb.1, %bb.2
@@ -553,6 +586,7 @@ body: |
; FAST-NEXT: [[ZEXT1:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC3]](s1)
; FAST-NEXT: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ZEXT1]](s32), [[C]], [[COPY]]
; FAST-NEXT: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32)
+ ;
; GREEDY-LABEL: name: phi_s1_s_scc_sbranch
; GREEDY: bb.0:
; GREEDY-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
@@ -647,6 +681,7 @@ body: |
; FAST-NEXT: [[ZEXT1:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC3]](s1)
; FAST-NEXT: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ZEXT1]](s32), [[C]], [[COPY]]
; FAST-NEXT: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32)
+ ;
; GREEDY-LABEL: name: phi_s1_scc_s_sbranch
; GREEDY: bb.0:
; GREEDY-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
@@ -743,6 +778,7 @@ body: |
; FAST-NEXT: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
; FAST-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY3]](s1), [[COPY4]], [[COPY5]]
; FAST-NEXT: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32)
+ ;
; GREEDY-LABEL: name: phi_s1_scc_v_sbranch
; GREEDY: bb.0:
; GREEDY-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
@@ -840,6 +876,7 @@ body: |
; FAST-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
; FAST-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY3]](s1), [[COPY4]], [[COPY]]
; FAST-NEXT: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32)
+ ;
; GREEDY-LABEL: name: phi_s1_v_scc_sbranch
; GREEDY: bb.0:
; GREEDY-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
@@ -918,21 +955,27 @@ body: |
; FAST-NEXT: [[ICMP1:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
; FAST-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP1]](s32)
; FAST-NEXT: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1)
+ ; FAST-NEXT: [[AMDGPU_COPY_SCC_VCC:%[0-9]+]]:sgpr(s32) = G_AMDGPU_COPY_SCC_VCC [[ICMP]](s1)
+ ; FAST-NEXT: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[AMDGPU_COPY_SCC_VCC]](s32)
+ ; FAST-NEXT: [[ANYEXT:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[TRUNC1]](s1)
; FAST-NEXT: G_BRCOND [[ZEXT]](s32), %bb.1
; FAST-NEXT: G_BR %bb.2
; FAST-NEXT: {{ $}}
; FAST-NEXT: bb.1:
; FAST-NEXT: successors: %bb.2(0x80000000)
; FAST-NEXT: {{ $}}
- ; FAST-NEXT: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY1]](s32)
- ; FAST-NEXT: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[TRUNC1]](s1)
+ ; FAST-NEXT: [[TRUNC2:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY1]](s32)
+ ; FAST-NEXT: [[ANYEXT1:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[TRUNC2]](s1)
; FAST-NEXT: G_BR %bb.2
; FAST-NEXT: {{ $}}
; FAST-NEXT: bb.2:
- ; FAST-NEXT: [[PHI:%[0-9]+]]:vcc(s1) = G_PHI [[ICMP]](s1), %bb.0, [[COPY4]](s1), %bb.1
+ ; FAST-NEXT: [[PHI:%[0-9]+]]:sgpr(s32) = G_PHI [[ANYEXT]](s32), %bb.0, [[ANYEXT1]](s32), %bb.1
+ ; FAST-NEXT: [[TRUNC3:%[0-9]+]]:sgpr(s1) = G_TRUNC [[PHI]](s32)
+ ; FAST-NEXT: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[TRUNC3]](s1)
; FAST-NEXT: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
- ; FAST-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[PHI]](s1), [[COPY5]], [[COPY]]
+ ; FAST-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY4]](s1), [[COPY5]], [[COPY]]
; FAST-NEXT: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32)
+ ;
; GREEDY-LABEL: name: phi_s1_vcc_s_sbranch
; GREEDY: bb.0:
; GREEDY-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
@@ -947,20 +990,25 @@ body: |
; GREEDY-NEXT: [[ICMP1:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
; GREEDY-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP1]](s32)
; GREEDY-NEXT: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1)
+ ; GREEDY-NEXT: [[AMDGPU_COPY_SCC_VCC:%[0-9]+]]:sgpr(s32) = G_AMDGPU_COPY_SCC_VCC [[ICMP]](s1)
+ ; GREEDY-NEXT: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[AMDGPU_COPY_SCC_VCC]](s32)
+ ; GREEDY-NEXT: [[ANYEXT:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[TRUNC1]](s1)
; GREEDY-NEXT: G_BRCOND [[ZEXT]](s32), %bb.1
; GREEDY-NEXT: G_BR %bb.2
; GREEDY-NEXT: {{ $}}
; GREEDY-NEXT: bb.1:
; GREEDY-NEXT: successors: %bb.2(0x80000000)
; GREEDY-NEXT: {{ $}}
- ; GREEDY-NEXT: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY1]](s32)
- ; GREEDY-NEXT: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[TRUNC1]](s1)
+ ; GREEDY-NEXT: [[TRUNC2:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY1]](s32)
+ ; GREEDY-NEXT: [[ANYEXT1:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[TRUNC2]](s1)
; GREEDY-NEXT: G_BR %bb.2
; GREEDY-NEXT: {{ $}}
; GREEDY-NEXT: bb.2:
- ; GREEDY-NEXT: [[PHI:%[0-9]+]]:vcc(s1) = G_PHI [[ICMP]](s1), %bb.0, [[COPY4]](s1), %bb.1
+ ; GREEDY-NEXT: [[PHI:%[0-9]+]]:sgpr(s32) = G_PHI [[ANYEXT]](s32), %bb.0, [[ANYEXT1]](s32), %bb.1
+ ; GREEDY-NEXT: [[TRUNC3:%[0-9]+]]:sgpr(s1) = G_TRUNC [[PHI]](s32)
+ ; GREEDY-NEXT: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[TRUNC3]](s1)
; GREEDY-NEXT: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
- ; GREEDY-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[PHI]](s1), [[COPY5]], [[COPY]]
+ ; GREEDY-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY4]](s1), [[COPY5]], [[COPY]]
; GREEDY-NEXT: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32)
bb.0:
successors: %bb.1, %bb.2
@@ -1007,23 +1055,27 @@ body: |
; FAST-NEXT: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
; FAST-NEXT: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
; FAST-NEXT: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC1]](s1)
- ; FAST-NEXT: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
+ ; FAST-NEXT: [[ANYEXT:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[TRUNC]](s1)
; FAST-NEXT: G_BRCOND [[ZEXT]](s32), %bb.1
; FAST-NEXT: G_BR %bb.2
; FAST-NEXT: {{ $}}
; FAST-NEXT: bb.1:
; FAST-NEXT: successors: %bb.2(0x80000000)
; FAST-NEXT: {{ $}}
- ; FAST-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
- ; FAST-NEXT: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY4]]
+ ; FAST-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
+ ; FAST-NEXT: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
+ ; FAST-NEXT: [[AMDGPU_COPY_SCC_VCC:%[0-9]+]]:sgpr(s32) = G_AMDGPU_COPY_SCC_VCC [[ICMP1]](s1)
+ ; FAST-NEXT: [[TRUNC2:%[0-9]+]]:sgpr(s1) = G_TRUNC [[AMDGPU_COPY_SCC_VCC]](s32)
+ ; FAST-NEXT: [[ANYEXT1:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[TRUNC2]](s1)
; FAST-NEXT: G_BR %bb.2
; FAST-NEXT: {{ $}}
; FAST-NEXT: bb.2:
- ; FAST-NEXT: [[PHI:%[0-9]+]]:vcc(s1) = G_PHI [[COPY3]](s1), %bb.0, [[ICMP1]](s1), %bb.1
- ; FAST-NEXT: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
- ; FAST-NEXT: [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
- ; FAST-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[PHI]](s1), [[COPY5]], [[COPY6]]
+ ; FAST-NEXT: [[PHI:%[0-9]+]]:sgpr(s32) = G_PHI [[ANYEXT]](s32), %bb.0, [[ANYEXT1]](s32), %bb.1
+ ; FAST-NEXT: [[TRUNC3:%[0-9]+]]:sgpr(s1) = G_TRUNC [[PHI]](s32)
+ ; FAST-NEXT: [[ZEXT1:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC3]](s1)
+ ; FAST-NEXT: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ZEXT1]](s32), [[C]], [[COPY]]
; FAST-NEXT: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32)
+ ;
; GREEDY-LABEL: name: phi_s1_s_vcc_sbranch
; GREEDY: bb.0:
; GREEDY-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
@@ -1037,22 +1089,25 @@ body: |
; GREEDY-NEXT: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
; GREEDY-NEXT: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
; GREEDY-NEXT: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC1]](s1)
- ; GREEDY-NEXT: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
+ ; GREEDY-NEXT: [[ANYEXT:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[TRUNC]](s1)
; GREEDY-NEXT: G_BRCOND [[ZEXT]](s32), %bb.1
; GREEDY-NEXT: G_BR %bb.2
; GREEDY-NEXT: {{ $}}
; GREEDY-NEXT: bb.1:
; GREEDY-NEXT: successors: %bb.2(0x80000000)
; GREEDY-NEXT: {{ $}}
- ; GREEDY-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
- ; GREEDY-NEXT: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY4]]
+ ; GREEDY-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
+ ; GREEDY-NEXT: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
+ ; GREEDY-NEXT: [[AMDGPU_COPY_SCC_VCC:%[0-9]+]]:sgpr(s32) = G_AMDGPU_COPY_SCC_VCC [[ICMP1]](s1)
+ ; GREEDY-NEXT: [[TRUNC2:%[0-9]+]]:sgpr(s1) = G_TRUNC [[AMDGPU_COPY_SCC_VCC]](s32)
+ ; GREEDY-NEXT: [[ANYEXT1:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[TRUNC2]](s1)
; GREEDY-NEXT: G_BR %bb.2
; GREEDY-NEXT: {{ $}}
; GREEDY-NEXT: bb.2:
- ; GREEDY-NEXT: [[PHI:%[0-9]+]]:vcc(s1) = G_PHI [[COPY3]](s1), %bb.0, [[ICMP1]](s1), %bb.1
- ; GREEDY-NEXT: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
- ; GREEDY-NEXT: [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
- ; GREEDY-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[PHI]](s1), [[COPY5]], [[COPY6]]
+ ; GREEDY-NEXT: [[PHI:%[0-9]+]]:sgpr(s32) = G_PHI [[ANYEXT]](s32), %bb.0, [[ANYEXT1]](s32), %bb.1
+ ; GREEDY-NEXT: [[TRUNC3:%[0-9]+]]:sgpr(s1) = G_TRUNC [[PHI]](s32)
+ ; GREEDY-NEXT: [[ZEXT1:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC3]](s1)
+ ; GREEDY-NEXT: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ZEXT1]](s32), [[C]], [[COPY]]
; GREEDY-NEXT: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32)
bb.0:
successors: %bb.1, %bb.2
@@ -1120,6 +1175,7 @@ body: |
; FAST-NEXT: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
; FAST-NEXT: [[SELECT1:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY4]](s1), [[COPY5]], [[COPY]]
; FAST-NEXT: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT1]](s32)
+ ;
; GREEDY-LABEL: name: phi_s1_vcc_v_sbranch
; GREEDY: bb.0:
; GREEDY-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
@@ -1220,6 +1276,7 @@ body: |
; FAST-NEXT: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
; FAST-NEXT: [[SELECT1:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY4]](s1), [[COPY5]], [[COPY]]
; FAST-NEXT: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT1]](s32)
+ ;
; GREEDY-LABEL: name: phi_s1_v_vcc_sbranch
; GREEDY: bb.0:
; GREEDY-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
@@ -1317,6 +1374,7 @@ body: |
; FAST-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
; FAST-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY3]](s1), [[COPY4]], [[COPY]]
; FAST-NEXT: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32)
+ ;
; GREEDY-LABEL: name: phi_s1_v_s_sbranch
; GREEDY: bb.0:
; GREEDY-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
@@ -1412,6 +1470,7 @@ body: |
; FAST-NEXT: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
; FAST-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY3]](s1), [[COPY4]], [[COPY5]]
; FAST-NEXT: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32)
+ ;
; GREEDY-LABEL: name: phi_s1_s_v_sbranch
; GREEDY: bb.0:
; GREEDY-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
@@ -1507,6 +1566,7 @@ body: |
; FAST-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
; FAST-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY3]](s1), [[COPY4]], [[COPY]]
; FAST-NEXT: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32)
+ ;
; GREEDY-LABEL: name: phi_s1_v_v_sbranch
; GREEDY: bb.0:
; GREEDY-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
@@ -1600,6 +1660,7 @@ body: |
; FAST-NEXT: [[ZEXT1:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC3]](s1)
; FAST-NEXT: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ZEXT1]](s32), [[C]], [[COPY]]
; FAST-NEXT: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32)
+ ;
; GREEDY-LABEL: name: phi_s1_s_s_sbranch
; GREEDY: bb.0:
; GREEDY-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
@@ -1676,7 +1737,7 @@ body: |
; FAST-NEXT: [[ICMP1:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
; FAST-NEXT: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP1]](s32)
; FAST-NEXT: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC1]](s1)
- ; FAST-NEXT: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
+ ; FAST-NEXT: [[ANYEXT:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[TRUNC]](s1)
; FAST-NEXT: G_BRCOND [[ZEXT]](s32), %bb.1
; FAST-NEXT: G_BR %bb.2
; FAST-NEXT: {{ $}}
@@ -1685,17 +1746,20 @@ body: |
; FAST-NEXT: {{ $}}
; FAST-NEXT: [[ICMP2:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]
; FAST-NEXT: [[TRUNC2:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP2]](s32)
- ; FAST-NEXT: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[TRUNC2]](s1)
+ ; FAST-NEXT: [[ANYEXT1:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[TRUNC2]](s1)
; FAST-NEXT: G_BR %bb.2
; FAST-NEXT: {{ $}}
; FAST-NEXT: bb.2:
- ; FAST-NEXT: [[PHI:%[0-9]+]]:vcc(s1) = G_PHI [[COPY3]](s1), %bb.0, [[COPY4]](s1), %bb.1
+ ; FAST-NEXT: [[PHI:%[0-9]+]]:sgpr(s32) = G_PHI [[ANYEXT]](s32), %bb.0, [[ANYEXT1]](s32), %bb.1
+ ; FAST-NEXT: [[TRUNC3:%[0-9]+]]:sgpr(s1) = G_TRUNC [[PHI]](s32)
+ ; FAST-NEXT: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[TRUNC3]](s1)
; FAST-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 123
- ; FAST-NEXT: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C1]](s32)
+ ; FAST-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C1]](s32)
; FAST-NEXT: [[C2:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 456
- ; FAST-NEXT: [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[C2]](s32)
- ; FAST-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[PHI]](s1), [[COPY5]], [[COPY6]]
+ ; FAST-NEXT: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C2]](s32)
+ ; FAST-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY3]](s1), [[COPY4]], [[COPY5]]
; FAST-NEXT: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32)
+ ;
; GREEDY-LABEL: name: phi_s1_vcc_result_scc_scc_sbranch
; GREEDY: bb.0:
; GREEDY-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
@@ -1710,7 +1774,7 @@ body: |
; GREEDY-NEXT: [[ICMP1:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
; GREEDY-NEXT: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP1]](s32)
; GREEDY-NEXT: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC1]](s1)
- ; GREEDY-NEXT: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
+ ; GREEDY-NEXT: [[ANYEXT:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[TRUNC]](s1)
; GREEDY-NEXT: G_BRCOND [[ZEXT]](s32), %bb.1
; GREEDY-NEXT: G_BR %bb.2
; GREEDY-NEXT: {{ $}}
@@ -1719,14 +1783,16 @@ body: |
; GREEDY-NEXT: {{ $}}
; GREEDY-NEXT: [[ICMP2:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]
; GREEDY-NEXT: [[TRUNC2:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP2]](s32)
- ; GREEDY-NEXT: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[TRUNC2]](s1)
+ ; GREEDY-NEXT: [[ANYEXT1:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[TRUNC2]](s1)
; GREEDY-NEXT: G_BR %bb.2
; GREEDY-NEXT: {{ $}}
; GREEDY-NEXT: bb.2:
- ; GREEDY-NEXT: [[PHI:%[0-9]+]]:vcc(s1) = G_PHI [[COPY3]](s1), %bb.0, [[COPY4]](s1), %bb.1
+ ; GREEDY-NEXT: [[PHI:%[0-9]+]]:sgpr(s32) = G_PHI [[ANYEXT]](s32), %bb.0, [[ANYEXT1]](s32), %bb.1
+ ; GREEDY-NEXT: [[TRUNC3:%[0-9]+]]:sgpr(s1) = G_TRUNC [[PHI]](s32)
+ ; GREEDY-NEXT: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[TRUNC3]](s1)
; GREEDY-NEXT: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 123
; GREEDY-NEXT: [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 456
- ; GREEDY-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[PHI]](s1), [[C1]], [[C2]]
+ ; GREEDY-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY3]](s1), [[C1]], [[C2]]
; GREEDY-NEXT: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32)
bb.0:
successors: %bb.1, %bb.2
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi.mir
index b5a04cef68807..b64c05826a738 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi.mir
@@ -33,6 +33,7 @@ body: |
; FAST-NEXT: [[PHI:%[0-9]+]]:sgpr(s32) = G_PHI [[COPY]](s32), %bb.0, [[COPY3]](s32), %bb.1
; FAST-NEXT: $sgpr0 = COPY [[PHI]](s32)
; FAST-NEXT: S_SETPC_B64 undef $sgpr30_sgpr31
+ ;
; GREEDY-LABEL: name: phi_s32_ss_sbranch
; GREEDY: bb.0:
; GREEDY-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
@@ -114,6 +115,7 @@ body: |
; FAST-NEXT: [[PHI:%[0-9]+]]:vgpr(s32) = G_PHI [[COPY]](s32), %bb.0, [[COPY3]](s32), %bb.1
; FAST-NEXT: $vgpr0 = COPY [[PHI]](s32)
; FAST-NEXT: S_SETPC_B64 undef $sgpr30_sgpr31
+ ;
; GREEDY-LABEL: name: phi_s32_sv_sbranch
; GREEDY: bb.0:
; GREEDY-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
@@ -195,6 +197,7 @@ body: |
; FAST-NEXT: [[PHI:%[0-9]+]]:vgpr(s32) = G_PHI [[COPY]](s32), %bb.0, [[COPY3]](s32), %bb.1
; FAST-NEXT: $vgpr0 = COPY [[PHI]](s32)
; FAST-NEXT: S_SETPC_B64 undef $sgpr30_sgpr31
+ ;
; GREEDY-LABEL: name: phi_s32_vs_sbranch
; GREEDY: bb.0:
; GREEDY-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
@@ -276,6 +279,7 @@ body: |
; FAST-NEXT: [[PHI:%[0-9]+]]:vgpr(s32) = G_PHI [[COPY]](s32), %bb.0, [[COPY3]](s32), %bb.1
; FAST-NEXT: $vgpr0 = COPY [[PHI]](s32)
; FAST-NEXT: S_SETPC_B64 undef $sgpr30_sgpr31
+ ;
; GREEDY-LABEL: name: phi_s32_vv_sbranch
; GREEDY: bb.0:
; GREEDY-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
@@ -355,6 +359,7 @@ body: |
; FAST-NEXT: [[PHI:%[0-9]+]]:sgpr(s32) = G_PHI [[COPY]](s32), %bb.0, [[COPY4]](s32), %bb.1
; FAST-NEXT: $sgpr0 = COPY [[PHI]](s32)
; FAST-NEXT: S_SETPC_B64 undef $sgpr30_sgpr31
+ ;
; GREEDY-LABEL: name: phi_s32_ss_vcc_sbranch
; GREEDY: bb.0:
; GREEDY-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
@@ -434,6 +439,7 @@ body: |
; FAST-NEXT: [[PHI:%[0-9]+]]:vgpr(s32) = G_PHI [[COPY]](s32), %bb.0, [[COPY4]](s32), %bb.1
; FAST-NEXT: $vgpr0 = COPY [[PHI]](s32)
; FAST-NEXT: S_SETPC_B64 undef $sgpr30_sgpr31
+ ;
; GREEDY-LABEL: name: phi_s32_sv_vcc_sbranch
; GREEDY: bb.0:
; GREEDY-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
@@ -513,6 +519,7 @@ body: |
; FAST-NEXT: [[PHI:%[0-9]+]]:vgpr(s32) = G_PHI [[COPY]](s32), %bb.0, [[COPY4]](s32), %bb.1
; FAST-NEXT: $vgpr0 = COPY [[PHI]](s32)
; FAST-NEXT: S_SETPC_B64 undef $sgpr30_sgpr31
+ ;
; GREEDY-LABEL: name: phi_s32_vs_vcc_sbranch
; GREEDY: bb.0:
; GREEDY-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
@@ -592,6 +599,7 @@ body: |
; FAST-NEXT: [[PHI:%[0-9]+]]:vgpr(s32) = G_PHI [[COPY]](s32), %bb.0, [[COPY4]](s32), %bb.1
; FAST-NEXT: $vgpr0 = COPY [[PHI]](s32)
; FAST-NEXT: S_SETPC_B64 undef $sgpr30_sgpr31
+ ;
; GREEDY-LABEL: name: phi_s32_vv_vcc_sbranch
; GREEDY: bb.0:
; GREEDY-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
@@ -679,6 +687,7 @@ body: |
; FAST-NEXT: [[ZEXT1:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC3]](s1)
; FAST-NEXT: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ZEXT1]](s32), [[C]], [[COPY]]
; FAST-NEXT: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32)
+ ;
; GREEDY-LABEL: name: phi_s1_scc_scc_sbranch
; GREEDY: bb.0:
; GREEDY-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
@@ -791,6 +800,7 @@ body: |
; FAST-NEXT: [[ZEXT2:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC5]](s1)
; FAST-NEXT: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ZEXT2]](s32), [[COPY]], [[COPY1]]
; FAST-NEXT: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32)
+ ;
; GREEDY-LABEL: name: phi_s1_scc_scc_scc_sbranch
; GREEDY: bb.0:
; GREEDY-NEXT: successors: %bb.1(0x40000000), %bb.3(0x40000000)
@@ -897,23 +907,27 @@ body: |
; FAST-NEXT: [[ICMP1:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
; FAST-NEXT: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP1]](s32)
; FAST-NEXT: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC1]](s1)
- ; FAST-NEXT: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
+ ; FAST-NEXT: [[ANYEXT:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[TRUNC]](s1)
; FAST-NEXT: G_BRCOND [[ZEXT]](s32), %bb.1
; FAST-NEXT: G_BR %bb.2
; FAST-NEXT: {{ $}}
; FAST-NEXT: bb.1:
; FAST-NEXT: successors: %bb.2(0x80000000)
; FAST-NEXT: {{ $}}
- ; FAST-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
- ; FAST-NEXT: [[ICMP2:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY4]]
+ ; FAST-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
+ ; FAST-NEXT: [[ICMP2:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
+ ; FAST-NEXT: [[AMDGPU_COPY_SCC_VCC:%[0-9]+]]:sgpr(s32) = G_AMDGPU_COPY_SCC_VCC [[ICMP2]](s1)
+ ; FAST-NEXT: [[TRUNC2:%[0-9]+]]:sgpr(s1) = G_TRUNC [[AMDGPU_COPY_SCC_VCC]](s32)
+ ; FAST-NEXT: [[ANYEXT1:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[TRUNC2]](s1)
; FAST-NEXT: G_BR %bb.2
; FAST-NEXT: {{ $}}
; FAST-NEXT: bb.2:
- ; FAST-NEXT: [[PHI:%[0-9]+]]:vcc(s1) = G_PHI [[COPY3]](s1), %bb.0, [[ICMP2]](s1), %bb.1
- ; FAST-NEXT: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
- ; FAST-NEXT: [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
- ; FAST-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[PHI]](s1), [[COPY5]], [[COPY6]]
+ ; FAST-NEXT: [[PHI:%[0-9]+]]:sgpr(s32) = G_PHI [[ANYEXT]](s32), %bb.0, [[ANYEXT1]](s32), %bb.1
+ ; FAST-NEXT: [[TRUNC3:%[0-9]+]]:sgpr(s1) = G_TRUNC [[PHI]](s32)
+ ; FAST-NEXT: [[ZEXT1:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC3]](s1)
+ ; FAST-NEXT: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ZEXT1]](s32), [[C]], [[COPY]]
; FAST-NEXT: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32)
+ ;
; GREEDY-LABEL: name: phi_s1_scc_vcc_sbranch
; GREEDY: bb.0:
; GREEDY-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
@@ -928,22 +942,25 @@ body: |
; GREEDY-NEXT: [[ICMP1:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
; GREEDY-NEXT: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP1]](s32)
; GREEDY-NEXT: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC1]](s1)
- ; GREEDY-NEXT: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
+ ; GREEDY-NEXT: [[ANYEXT:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[TRUNC]](s1)
; GREEDY-NEXT: G_BRCOND [[ZEXT]](s32), %bb.1
; GREEDY-NEXT: G_BR %bb.2
; GREEDY-NEXT: {{ $}}
; GREEDY-NEXT: bb.1:
; GREEDY-NEXT: successors: %bb.2(0x80000000)
; GREEDY-NEXT: {{ $}}
- ; GREEDY-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
- ; GREEDY-NEXT: [[ICMP2:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY4]]
+ ; GREEDY-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
+ ; GREEDY-NEXT: [[ICMP2:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
+ ; GREEDY-NEXT: [[AMDGPU_COPY_SCC_VCC:%[0-9]+]]:sgpr(s32) = G_AMDGPU_COPY_SCC_VCC [[ICMP2]](s1)
+ ; GREEDY-NEXT: [[TRUNC2:%[0-9]+]]:sgpr(s1) = G_TRUNC [[AMDGPU_COPY_SCC_VCC]](s32)
+ ; GREEDY-NEXT: [[ANYEXT1:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[TRUNC2]](s1)
; GREEDY-NEXT: G_BR %bb.2
; GREEDY-NEXT: {{ $}}
; GREEDY-NEXT: bb.2:
- ; GREEDY-NEXT: [[PHI:%[0-9]+]]:vcc(s1) = G_PHI [[COPY3]](s1), %bb.0, [[ICMP2]](s1), %bb.1
- ; GREEDY-NEXT: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
- ; GREEDY-NEXT: [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
- ; GREEDY-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[PHI]](s1), [[COPY5]], [[COPY6]]
+ ; GREEDY-NEXT: [[PHI:%[0-9]+]]:sgpr(s32) = G_PHI [[ANYEXT]](s32), %bb.0, [[ANYEXT1]](s32), %bb.1
+ ; GREEDY-NEXT: [[TRUNC3:%[0-9]+]]:sgpr(s1) = G_TRUNC [[PHI]](s32)
+ ; GREEDY-NEXT: [[ZEXT1:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC3]](s1)
+ ; GREEDY-NEXT: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ZEXT1]](s32), [[C]], [[COPY]]
; GREEDY-NEXT: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32)
bb.0:
successors: %bb.1, %bb.2
@@ -991,6 +1008,9 @@ body: |
; FAST-NEXT: [[ICMP1:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
; FAST-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP1]](s32)
; FAST-NEXT: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1)
+ ; FAST-NEXT: [[AMDGPU_COPY_SCC_VCC:%[0-9]+]]:sgpr(s32) = G_AMDGPU_COPY_SCC_VCC [[ICMP]](s1)
+ ; FAST-NEXT: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[AMDGPU_COPY_SCC_VCC]](s32)
+ ; FAST-NEXT: [[ANYEXT:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[TRUNC1]](s1)
; FAST-NEXT: G_BRCOND [[ZEXT]](s32), %bb.1
; FAST-NEXT: G_BR %bb.2
; FAST-NEXT: {{ $}}
@@ -998,16 +1018,17 @@ body: |
; FAST-NEXT: successors: %bb.2(0x80000000)
; FAST-NEXT: {{ $}}
; FAST-NEXT: [[ICMP2:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]
- ; FAST-NEXT: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP2]](s32)
- ; FAST-NEXT: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[TRUNC1]](s1)
+ ; FAST-NEXT: [[TRUNC2:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP2]](s32)
+ ; FAST-NEXT: [[ANYEXT1:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[TRUNC2]](s1)
; FAST-NEXT: G_BR %bb.2
; FAST-NEXT: {{ $}}
; FAST-NEXT: bb.2:
- ; FAST-NEXT: [[PHI:%[0-9]+]]:vcc(s1) = G_PHI [[ICMP]](s1), %bb.0, [[COPY4]](s1), %bb.1
- ; FAST-NEXT: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
- ; FAST-NEXT: [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
- ; FAST-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[PHI]](s1), [[COPY5]], [[COPY6]]
+ ; FAST-NEXT: [[PHI:%[0-9]+]]:sgpr(s32) = G_PHI [[ANYEXT]](s32), %bb.0, [[ANYEXT1]](s32), %bb.1
+ ; FAST-NEXT: [[TRUNC3:%[0-9]+]]:sgpr(s1) = G_TRUNC [[PHI]](s32)
+ ; FAST-NEXT: [[ZEXT1:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC3]](s1)
+ ; FAST-NEXT: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ZEXT1]](s32), [[C]], [[COPY1]]
; FAST-NEXT: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32)
+ ;
; GREEDY-LABEL: name: phi_s1_vcc_scc_sbranch
; GREEDY: bb.0:
; GREEDY-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
@@ -1022,6 +1043,9 @@ body: |
; GREEDY-NEXT: [[ICMP1:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
; GREEDY-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP1]](s32)
; GREEDY-NEXT: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1)
+ ; GREEDY-NEXT: [[AMDGPU_COPY_SCC_VCC:%[0-9]+]]:sgpr(s32) = G_AMDGPU_COPY_SCC_VCC [[ICMP]](s1)
+ ; GREEDY-NEXT: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[AMDGPU_COPY_SCC_VCC]](s32)
+ ; GREEDY-NEXT: [[ANYEXT:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[TRUNC1]](s1)
; GREEDY-NEXT: G_BRCOND [[ZEXT]](s32), %bb.1
; GREEDY-NEXT: G_BR %bb.2
; GREEDY-NEXT: {{ $}}
@@ -1029,15 +1053,15 @@ body: |
; GREEDY-NEXT: successors: %bb.2(0x80000000)
; GREEDY-NEXT: {{ $}}
; GREEDY-NEXT: [[ICMP2:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]
- ; GREEDY-NEXT: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP2]](s32)
- ; GREEDY-NEXT: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[TRUNC1]](s1)
+ ; GREEDY-NEXT: [[TRUNC2:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP2]](s32)
+ ; GREEDY-NEXT: [[ANYEXT1:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[TRUNC2]](s1)
; GREEDY-NEXT: G_BR %bb.2
; GREEDY-NEXT: {{ $}}
; GREEDY-NEXT: bb.2:
- ; GREEDY-NEXT: [[PHI:%[0-9]+]]:vcc(s1) = G_PHI [[ICMP]](s1), %bb.0, [[COPY4]](s1), %bb.1
- ; GREEDY-NEXT: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
- ; GREEDY-NEXT: [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
- ; GREEDY-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[PHI]](s1), [[COPY5]], [[COPY6]]
+ ; GREEDY-NEXT: [[PHI:%[0-9]+]]:sgpr(s32) = G_PHI [[ANYEXT]](s32), %bb.0, [[ANYEXT1]](s32), %bb.1
+ ; GREEDY-NEXT: [[TRUNC3:%[0-9]+]]:sgpr(s1) = G_TRUNC [[PHI]](s32)
+ ; GREEDY-NEXT: [[ZEXT1:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC3]](s1)
+ ; GREEDY-NEXT: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ZEXT1]](s32), [[C]], [[COPY1]]
; GREEDY-NEXT: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32)
bb.0:
successors: %bb.1, %bb.2
@@ -1085,6 +1109,9 @@ body: |
; FAST-NEXT: [[ICMP1:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
; FAST-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP1]](s32)
; FAST-NEXT: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1)
+ ; FAST-NEXT: [[AMDGPU_COPY_SCC_VCC:%[0-9]+]]:sgpr(s32) = G_AMDGPU_COPY_SCC_VCC [[ICMP]](s1)
+ ; FAST-NEXT: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[AMDGPU_COPY_SCC_VCC]](s32)
+ ; FAST-NEXT: [[ANYEXT:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[TRUNC1]](s1)
; FAST-NEXT: G_BRCOND [[ZEXT]](s32), %bb.1
; FAST-NEXT: G_BR %bb.2
; FAST-NEXT: {{ $}}
@@ -1093,13 +1120,19 @@ body: |
; FAST-NEXT: {{ $}}
; FAST-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
; FAST-NEXT: [[ICMP2:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY4]]
+ ; FAST-NEXT: [[AMDGPU_COPY_SCC_VCC1:%[0-9]+]]:sgpr(s32) = G_AMDGPU_COPY_SCC_VCC [[ICMP2]](s1)
+ ; FAST-NEXT: [[TRUNC2:%[0-9]+]]:sgpr(s1) = G_TRUNC [[AMDGPU_COPY_SCC_VCC1]](s32)
+ ; FAST-NEXT: [[ANYEXT1:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[TRUNC2]](s1)
; FAST-NEXT: G_BR %bb.2
; FAST-NEXT: {{ $}}
; FAST-NEXT: bb.2:
- ; FAST-NEXT: [[PHI:%[0-9]+]]:vcc(s1) = G_PHI [[ICMP]](s1), %bb.0, [[ICMP2]](s1), %bb.1
- ; FAST-NEXT: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
- ; FAST-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[PHI]](s1), [[COPY5]], [[COPY]]
+ ; FAST-NEXT: [[PHI:%[0-9]+]]:sgpr(s32) = G_PHI [[ANYEXT]](s32), %bb.0, [[ANYEXT1]](s32), %bb.1
+ ; FAST-NEXT: [[TRUNC3:%[0-9]+]]:sgpr(s1) = G_TRUNC [[PHI]](s32)
+ ; FAST-NEXT: [[COPY5:%[0-9]+]]:vcc(s1) = COPY [[TRUNC3]](s1)
+ ; FAST-NEXT: [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
+ ; FAST-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY5]](s1), [[COPY6]], [[COPY]]
; FAST-NEXT: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32)
+ ;
; GREEDY-LABEL: name: phi_s1_vcc_vcc_sbranch
; GREEDY: bb.0:
; GREEDY-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
@@ -1114,6 +1147,9 @@ body: |
; GREEDY-NEXT: [[ICMP1:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
; GREEDY-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP1]](s32)
; GREEDY-NEXT: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1)
+ ; GREEDY-NEXT: [[AMDGPU_COPY_SCC_VCC:%[0-9]+]]:sgpr(s32) = G_AMDGPU_COPY_SCC_VCC [[ICMP]](s1)
+ ; GREEDY-NEXT: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[AMDGPU_COPY_SCC_VCC]](s32)
+ ; GREEDY-NEXT: [[ANYEXT:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[TRUNC1]](s1)
; GREEDY-NEXT: G_BRCOND [[ZEXT]](s32), %bb.1
; GREEDY-NEXT: G_BR %bb.2
; GREEDY-NEXT: {{ $}}
@@ -1122,12 +1158,17 @@ body: |
; GREEDY-NEXT: {{ $}}
; GREEDY-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
; GREEDY-NEXT: [[ICMP2:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY4]]
+ ; GREEDY-NEXT: [[AMDGPU_COPY_SCC_VCC1:%[0-9]+]]:sgpr(s32) = G_AMDGPU_COPY_SCC_VCC [[ICMP2]](s1)
+ ; GREEDY-NEXT: [[TRUNC2:%[0-9]+]]:sgpr(s1) = G_TRUNC [[AMDGPU_COPY_SCC_VCC1]](s32)
+ ; GREEDY-NEXT: [[ANYEXT1:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[TRUNC2]](s1)
; GREEDY-NEXT: G_BR %bb.2
; GREEDY-NEXT: {{ $}}
; GREEDY-NEXT: bb.2:
- ; GREEDY-NEXT: [[PHI:%[0-9]+]]:vcc(s1) = G_PHI [[ICMP]](s1), %bb.0, [[ICMP2]](s1), %bb.1
- ; GREEDY-NEXT: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
- ; GREEDY-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[PHI]](s1), [[COPY5]], [[COPY]]
+ ; GREEDY-NEXT: [[PHI:%[0-9]+]]:sgpr(s32) = G_PHI [[ANYEXT]](s32), %bb.0, [[ANYEXT1]](s32), %bb.1
+ ; GREEDY-NEXT: [[TRUNC3:%[0-9]+]]:sgpr(s1) = G_TRUNC [[PHI]](s32)
+ ; GREEDY-NEXT: [[COPY5:%[0-9]+]]:vcc(s1) = COPY [[TRUNC3]](s1)
+ ; GREEDY-NEXT: [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
+ ; GREEDY-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY5]](s1), [[COPY6]], [[COPY]]
; GREEDY-NEXT: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32)
bb.0:
successors: %bb.1, %bb.2
@@ -1192,6 +1233,7 @@ body: |
; FAST-NEXT: [[ZEXT1:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC3]](s1)
; FAST-NEXT: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ZEXT1]](s32), [[C]], [[COPY]]
; FAST-NEXT: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32)
+ ;
; GREEDY-LABEL: name: phi_s1_s_scc_sbranch
; GREEDY: bb.0:
; GREEDY-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
@@ -1286,6 +1328,7 @@ body: |
; FAST-NEXT: [[ZEXT1:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC3]](s1)
; FAST-NEXT: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ZEXT1]](s32), [[C]], [[COPY]]
; FAST-NEXT: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32)
+ ;
; GREEDY-LABEL: name: phi_s1_scc_s_sbranch
; GREEDY: bb.0:
; GREEDY-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
@@ -1382,6 +1425,7 @@ body: |
; FAST-NEXT: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
; FAST-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY3]](s1), [[COPY4]], [[COPY5]]
; FAST-NEXT: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32)
+ ;
; GREEDY-LABEL: name: phi_s1_scc_v_sbranch
; GREEDY: bb.0:
; GREEDY-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
@@ -1479,6 +1523,7 @@ body: |
; FAST-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
; FAST-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY3]](s1), [[COPY4]], [[COPY]]
; FAST-NEXT: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32)
+ ;
; GREEDY-LABEL: name: phi_s1_v_scc_sbranch
; GREEDY: bb.0:
; GREEDY-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
@@ -1557,21 +1602,27 @@ body: |
; FAST-NEXT: [[ICMP1:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
; FAST-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP1]](s32)
; FAST-NEXT: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1)
+ ; FAST-NEXT: [[AMDGPU_COPY_SCC_VCC:%[0-9]+]]:sgpr(s32) = G_AMDGPU_COPY_SCC_VCC [[ICMP]](s1)
+ ; FAST-NEXT: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[AMDGPU_COPY_SCC_VCC]](s32)
+ ; FAST-NEXT: [[ANYEXT:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[TRUNC1]](s1)
; FAST-NEXT: G_BRCOND [[ZEXT]](s32), %bb.1
; FAST-NEXT: G_BR %bb.2
; FAST-NEXT: {{ $}}
; FAST-NEXT: bb.1:
; FAST-NEXT: successors: %bb.2(0x80000000)
; FAST-NEXT: {{ $}}
- ; FAST-NEXT: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY1]](s32)
- ; FAST-NEXT: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[TRUNC1]](s1)
+ ; FAST-NEXT: [[TRUNC2:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY1]](s32)
+ ; FAST-NEXT: [[ANYEXT1:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[TRUNC2]](s1)
; FAST-NEXT: G_BR %bb.2
; FAST-NEXT: {{ $}}
; FAST-NEXT: bb.2:
- ; FAST-NEXT: [[PHI:%[0-9]+]]:vcc(s1) = G_PHI [[ICMP]](s1), %bb.0, [[COPY4]](s1), %bb.1
+ ; FAST-NEXT: [[PHI:%[0-9]+]]:sgpr(s32) = G_PHI [[ANYEXT]](s32), %bb.0, [[ANYEXT1]](s32), %bb.1
+ ; FAST-NEXT: [[TRUNC3:%[0-9]+]]:sgpr(s1) = G_TRUNC [[PHI]](s32)
+ ; FAST-NEXT: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[TRUNC3]](s1)
; FAST-NEXT: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
- ; FAST-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[PHI]](s1), [[COPY5]], [[COPY]]
+ ; FAST-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY4]](s1), [[COPY5]], [[COPY]]
; FAST-NEXT: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32)
+ ;
; GREEDY-LABEL: name: phi_s1_vcc_s_sbranch
; GREEDY: bb.0:
; GREEDY-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
@@ -1586,20 +1637,25 @@ body: |
; GREEDY-NEXT: [[ICMP1:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
; GREEDY-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP1]](s32)
; GREEDY-NEXT: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1)
+ ; GREEDY-NEXT: [[AMDGPU_COPY_SCC_VCC:%[0-9]+]]:sgpr(s32) = G_AMDGPU_COPY_SCC_VCC [[ICMP]](s1)
+ ; GREEDY-NEXT: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[AMDGPU_COPY_SCC_VCC]](s32)
+ ; GREEDY-NEXT: [[ANYEXT:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[TRUNC1]](s1)
; GREEDY-NEXT: G_BRCOND [[ZEXT]](s32), %bb.1
; GREEDY-NEXT: G_BR %bb.2
; GREEDY-NEXT: {{ $}}
; GREEDY-NEXT: bb.1:
; GREEDY-NEXT: successors: %bb.2(0x80000000)
; GREEDY-NEXT: {{ $}}
- ; GREEDY-NEXT: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY1]](s32)
- ; GREEDY-NEXT: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[TRUNC1]](s1)
+ ; GREEDY-NEXT: [[TRUNC2:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY1]](s32)
+ ; GREEDY-NEXT: [[ANYEXT1:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[TRUNC2]](s1)
; GREEDY-NEXT: G_BR %bb.2
; GREEDY-NEXT: {{ $}}
; GREEDY-NEXT: bb.2:
- ; GREEDY-NEXT: [[PHI:%[0-9]+]]:vcc(s1) = G_PHI [[ICMP]](s1), %bb.0, [[COPY4]](s1), %bb.1
+ ; GREEDY-NEXT: [[PHI:%[0-9]+]]:sgpr(s32) = G_PHI [[ANYEXT]](s32), %bb.0, [[ANYEXT1]](s32), %bb.1
+ ; GREEDY-NEXT: [[TRUNC3:%[0-9]+]]:sgpr(s1) = G_TRUNC [[PHI]](s32)
+ ; GREEDY-NEXT: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[TRUNC3]](s1)
; GREEDY-NEXT: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
- ; GREEDY-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[PHI]](s1), [[COPY5]], [[COPY]]
+ ; GREEDY-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY4]](s1), [[COPY5]], [[COPY]]
; GREEDY-NEXT: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32)
bb.0:
successors: %bb.1, %bb.2
@@ -1646,23 +1702,27 @@ body: |
; FAST-NEXT: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
; FAST-NEXT: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
; FAST-NEXT: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC1]](s1)
- ; FAST-NEXT: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
+ ; FAST-NEXT: [[ANYEXT:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[TRUNC]](s1)
; FAST-NEXT: G_BRCOND [[ZEXT]](s32), %bb.1
; FAST-NEXT: G_BR %bb.2
; FAST-NEXT: {{ $}}
; FAST-NEXT: bb.1:
; FAST-NEXT: successors: %bb.2(0x80000000)
; FAST-NEXT: {{ $}}
- ; FAST-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
- ; FAST-NEXT: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY4]]
+ ; FAST-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
+ ; FAST-NEXT: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
+ ; FAST-NEXT: [[AMDGPU_COPY_SCC_VCC:%[0-9]+]]:sgpr(s32) = G_AMDGPU_COPY_SCC_VCC [[ICMP1]](s1)
+ ; FAST-NEXT: [[TRUNC2:%[0-9]+]]:sgpr(s1) = G_TRUNC [[AMDGPU_COPY_SCC_VCC]](s32)
+ ; FAST-NEXT: [[ANYEXT1:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[TRUNC2]](s1)
; FAST-NEXT: G_BR %bb.2
; FAST-NEXT: {{ $}}
; FAST-NEXT: bb.2:
- ; FAST-NEXT: [[PHI:%[0-9]+]]:vcc(s1) = G_PHI [[COPY3]](s1), %bb.0, [[ICMP1]](s1), %bb.1
- ; FAST-NEXT: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
- ; FAST-NEXT: [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
- ; FAST-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[PHI]](s1), [[COPY5]], [[COPY6]]
+ ; FAST-NEXT: [[PHI:%[0-9]+]]:sgpr(s32) = G_PHI [[ANYEXT]](s32), %bb.0, [[ANYEXT1]](s32), %bb.1
+ ; FAST-NEXT: [[TRUNC3:%[0-9]+]]:sgpr(s1) = G_TRUNC [[PHI]](s32)
+ ; FAST-NEXT: [[ZEXT1:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC3]](s1)
+ ; FAST-NEXT: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ZEXT1]](s32), [[C]], [[COPY]]
; FAST-NEXT: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32)
+ ;
; GREEDY-LABEL: name: phi_s1_s_vcc_sbranch
; GREEDY: bb.0:
; GREEDY-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
@@ -1676,22 +1736,25 @@ body: |
; GREEDY-NEXT: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
; GREEDY-NEXT: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
; GREEDY-NEXT: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC1]](s1)
- ; GREEDY-NEXT: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
+ ; GREEDY-NEXT: [[ANYEXT:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[TRUNC]](s1)
; GREEDY-NEXT: G_BRCOND [[ZEXT]](s32), %bb.1
; GREEDY-NEXT: G_BR %bb.2
; GREEDY-NEXT: {{ $}}
; GREEDY-NEXT: bb.1:
; GREEDY-NEXT: successors: %bb.2(0x80000000)
; GREEDY-NEXT: {{ $}}
- ; GREEDY-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
- ; GREEDY-NEXT: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY4]]
+ ; GREEDY-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
+ ; GREEDY-NEXT: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
+ ; GREEDY-NEXT: [[AMDGPU_COPY_SCC_VCC:%[0-9]+]]:sgpr(s32) = G_AMDGPU_COPY_SCC_VCC [[ICMP1]](s1)
+ ; GREEDY-NEXT: [[TRUNC2:%[0-9]+]]:sgpr(s1) = G_TRUNC [[AMDGPU_COPY_SCC_VCC]](s32)
+ ; GREEDY-NEXT: [[ANYEXT1:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[TRUNC2]](s1)
; GREEDY-NEXT: G_BR %bb.2
; GREEDY-NEXT: {{ $}}
; GREEDY-NEXT: bb.2:
- ; GREEDY-NEXT: [[PHI:%[0-9]+]]:vcc(s1) = G_PHI [[COPY3]](s1), %bb.0, [[ICMP1]](s1), %bb.1
- ; GREEDY-NEXT: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
- ; GREEDY-NEXT: [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
- ; GREEDY-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[PHI]](s1), [[COPY5]], [[COPY6]]
+ ; GREEDY-NEXT: [[PHI:%[0-9]+]]:sgpr(s32) = G_PHI [[ANYEXT]](s32), %bb.0, [[ANYEXT1]](s32), %bb.1
+ ; GREEDY-NEXT: [[TRUNC3:%[0-9]+]]:sgpr(s1) = G_TRUNC [[PHI]](s32)
+ ; GREEDY-NEXT: [[ZEXT1:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC3]](s1)
+ ; GREEDY-NEXT: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ZEXT1]](s32), [[C]], [[COPY]]
; GREEDY-NEXT: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32)
bb.0:
successors: %bb.1, %bb.2
@@ -1759,6 +1822,7 @@ body: |
; FAST-NEXT: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
; FAST-NEXT: [[SELECT1:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY4]](s1), [[COPY5]], [[COPY]]
; FAST-NEXT: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT1]](s32)
+ ;
; GREEDY-LABEL: name: phi_s1_vcc_v_sbranch
; GREEDY: bb.0:
; GREEDY-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
@@ -1859,6 +1923,7 @@ body: |
; FAST-NEXT: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
; FAST-NEXT: [[SELECT1:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY4]](s1), [[COPY5]], [[COPY]]
; FAST-NEXT: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT1]](s32)
+ ;
; GREEDY-LABEL: name: phi_s1_v_vcc_sbranch
; GREEDY: bb.0:
; GREEDY-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
@@ -1956,6 +2021,7 @@ body: |
; FAST-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
; FAST-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY3]](s1), [[COPY4]], [[COPY]]
; FAST-NEXT: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32)
+ ;
; GREEDY-LABEL: name: phi_s1_v_s_sbranch
; GREEDY: bb.0:
; GREEDY-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
@@ -2051,6 +2117,7 @@ body: |
; FAST-NEXT: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
; FAST-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY3]](s1), [[COPY4]], [[COPY5]]
; FAST-NEXT: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32)
+ ;
; GREEDY-LABEL: name: phi_s1_s_v_sbranch
; GREEDY: bb.0:
; GREEDY-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
@@ -2146,6 +2213,7 @@ body: |
; FAST-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
; FAST-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY3]](s1), [[COPY4]], [[COPY]]
; FAST-NEXT: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32)
+ ;
; GREEDY-LABEL: name: phi_s1_v_v_sbranch
; GREEDY: bb.0:
; GREEDY-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
@@ -2239,6 +2307,7 @@ body: |
; FAST-NEXT: [[ZEXT1:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC3]](s1)
; FAST-NEXT: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ZEXT1]](s32), [[C]], [[COPY]]
; FAST-NEXT: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32)
+ ;
; GREEDY-LABEL: name: phi_s1_s_s_sbranch
; GREEDY: bb.0:
; GREEDY-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
@@ -2326,6 +2395,7 @@ body: |
; FAST-NEXT: {{ $}}
; FAST-NEXT: bb.2:
; FAST-NEXT: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[PHI]](s32)
+ ;
; GREEDY-LABEL: name: phi_s32_s_loop_v_sbranch
; GREEDY: bb.0:
; GREEDY-NEXT: successors: %bb.1(0x80000000)
@@ -2405,6 +2475,7 @@ body: |
; FAST-NEXT: {{ $}}
; FAST-NEXT: bb.2:
; FAST-NEXT: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[PHI]](s32)
+ ;
; GREEDY-LABEL: name: phi_s32_s_loop_s_sbranch
; GREEDY: bb.0:
; GREEDY-NEXT: successors: %bb.1(0x80000000)
@@ -2485,6 +2556,7 @@ body: |
; FAST-NEXT: {{ $}}
; FAST-NEXT: [[PHI1:%[0-9]+]]:vgpr(s32) = G_PHI [[COPY]](s32), %bb.0, [[PHI]](s32), %bb.1
; FAST-NEXT: G_BR %bb.1
+ ;
; GREEDY-LABEL: name: phi_s32_ss_sbranch_cycle
; GREEDY: bb.0:
; GREEDY-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
@@ -2566,6 +2638,7 @@ body: |
; FAST-NEXT: {{ $}}
; FAST-NEXT: [[PHI1:%[0-9]+]]:vgpr(s32) = G_PHI [[COPY]](s32), %bb.0, [[PHI]](s32), %bb.1
; FAST-NEXT: G_BR %bb.1
+ ;
; GREEDY-LABEL: name: phi_s32_vs_sbranch_cycle
; GREEDY: bb.0:
; GREEDY-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
@@ -2646,6 +2719,7 @@ body: |
; FAST-NEXT: [[PHI:%[0-9]+]]:agpr(s32) = G_PHI [[COPY]](s32), %bb.0, [[COPY3]](s32), %bb.1
; FAST-NEXT: $agpr0 = COPY [[PHI]](s32)
; FAST-NEXT: S_SETPC_B64 undef $sgpr30_sgpr31
+ ;
; GREEDY-LABEL: name: phi_s32_aa_sbranch
; GREEDY: bb.0:
; GREEDY-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
@@ -2727,6 +2801,7 @@ body: |
; FAST-NEXT: [[PHI:%[0-9]+]]:vgpr(s32) = G_PHI [[COPY]](s32), %bb.0, [[COPY3]](s32), %bb.1
; FAST-NEXT: $agpr0 = COPY [[PHI]](s32)
; FAST-NEXT: S_SETPC_B64 undef $sgpr30_sgpr31
+ ;
; GREEDY-LABEL: name: phi_s32_av_sbranch
; GREEDY: bb.0:
; GREEDY-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
@@ -2807,6 +2882,7 @@ body: |
; FAST-NEXT: [[PHI:%[0-9]+]]:vgpr(s32) = G_PHI [[COPY]](s32), %bb.0, [[COPY3]](s32), %bb.1
; FAST-NEXT: $agpr0 = COPY [[PHI]](s32)
; FAST-NEXT: S_SETPC_B64 undef $sgpr30_sgpr31
+ ;
; GREEDY-LABEL: name: phi_s32_va_sbranch
; GREEDY: bb.0:
; GREEDY-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
@@ -2888,6 +2964,7 @@ body: |
; FAST-NEXT: [[PHI:%[0-9]+]]:vgpr(s32) = G_PHI [[COPY]](s32), %bb.0, [[COPY3]](s32), %bb.1
; FAST-NEXT: $agpr0 = COPY [[PHI]](s32)
; FAST-NEXT: S_SETPC_B64 undef $sgpr30_sgpr31
+ ;
; GREEDY-LABEL: name: phi_s32_as_sbranch
; GREEDY: bb.0:
; GREEDY-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
@@ -2969,6 +3046,7 @@ body: |
; FAST-NEXT: [[PHI:%[0-9]+]]:vgpr(s32) = G_PHI [[COPY]](s32), %bb.0, [[COPY3]](s32), %bb.1
; FAST-NEXT: $agpr0 = COPY [[PHI]](s32)
; FAST-NEXT: S_SETPC_B64 undef $sgpr30_sgpr31
+ ;
; GREEDY-LABEL: name: phi_s32_sa_sbranch
; GREEDY: bb.0:
; GREEDY-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/vcc-s1-phi.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/vcc-s1-phi.ll
new file mode 100644
index 0000000000000..b358e9cc19b1c
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/vcc-s1-phi.ll
@@ -0,0 +1,198 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -global-isel-abort=1 < %s | FileCheck -check-prefix=GFX9 %s
+; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -global-isel-abort=1 < %s | FileCheck -check-prefix=GFX10 %s
+
+; Test that VCC S1 phis are correctly handled by converting to SGPR bank.
+; Previously, VCC S1 phis would fail instruction selection with:
+; "cannot select: %N:sreg_64_xexec(s1) = G_PHI ..."
+
+define void @vcc_s1_phi_from_vgpr_compare() {
+; GFX9-LABEL: vcc_s1_phi_from_vgpr_compare:
+; GFX9: ; %bb.0: ; %entry
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_mov_b32_e32 v0, 0
+; GFX9-NEXT: ds_read_u16 v0, v0
+; GFX9-NEXT: v_mov_b32_e32 v1, 0x100
+; GFX9-NEXT: s_mov_b32 s4, 0
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: v_cmp_eq_u16_e32 vcc, v0, v1
+; GFX9-NEXT: s_cbranch_vccnz .LBB0_2
+; GFX9-NEXT: ; %bb.1: ; %compare
+; GFX9-NEXT: v_mov_b32_e32 v1, 0x200
+; GFX9-NEXT: v_cmp_eq_u16_e32 vcc, v0, v1
+; GFX9-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX9-NEXT: s_cselect_b32 s4, 1, 0
+; GFX9-NEXT: .LBB0_2: ; %exit
+; GFX9-NEXT: s_xor_b32 s4, s4, 1
+; GFX9-NEXT: s_cmp_lg_u32 s4, 0
+; GFX9-NEXT: s_cbranch_scc1 .LBB0_4
+; GFX9-NEXT: ; %bb.3: ; %store
+; GFX9-NEXT: v_mov_b32_e32 v0, 42
+; GFX9-NEXT: v_mov_b32_e32 v1, 0
+; GFX9-NEXT: ds_write_b16 v1, v0
+; GFX9-NEXT: .LBB0_4: ; %end
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: vcc_s1_phi_from_vgpr_compare:
+; GFX10: ; %bb.0: ; %entry
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_mov_b32_e32 v0, 0
+; GFX10-NEXT: s_mov_b32 s4, 0
+; GFX10-NEXT: ds_read_u16 v0, v0
+; GFX10-NEXT: s_waitcnt lgkmcnt(0)
+; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x100, v0
+; GFX10-NEXT: s_cbranch_vccnz .LBB0_2
+; GFX10-NEXT: ; %bb.1: ; %compare
+; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x200, v0
+; GFX10-NEXT: s_cmp_lg_u32 vcc_lo, 0
+; GFX10-NEXT: s_cselect_b32 s4, 1, 0
+; GFX10-NEXT: .LBB0_2: ; %exit
+; GFX10-NEXT: s_xor_b32 s4, s4, 1
+; GFX10-NEXT: s_cmp_lg_u32 s4, 0
+; GFX10-NEXT: s_cbranch_scc1 .LBB0_4
+; GFX10-NEXT: ; %bb.3: ; %store
+; GFX10-NEXT: v_mov_b32_e32 v0, 42
+; GFX10-NEXT: v_mov_b32_e32 v1, 0
+; GFX10-NEXT: ds_write_b16 v1, v0
+; GFX10-NEXT: .LBB0_4: ; %end
+; GFX10-NEXT: s_waitcnt lgkmcnt(0)
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %ld = load i16, ptr addrspace(3) null, align 2
+ %cmp1 = icmp eq i16 %ld, 256
+ br i1 %cmp1, label %exit, label %compare
+
+compare:
+ %cmp2 = icmp eq i16 %ld, 512
+ br label %exit
+
+exit:
+ ; This phi has VCC S1 inputs from VGPR compares. Previously failed with
+ ; "cannot select: %N:sreg_64_xexec(s1) = G_PHI ..."
+ %phi = phi i1 [ false, %entry ], [ %cmp2, %compare ]
+ br i1 %phi, label %store, label %end
+
+store:
+ store i16 42, ptr addrspace(3) null, align 2
+ br label %end
+
+end:
+ ret void
+}
+
+; Test with switch statement (similar to original reproducer)
+ at G = external global i1
+
+define void @vcc_s1_phi_switch() {
+; GFX9-LABEL: vcc_s1_phi_switch:
+; GFX9: ; %bb.0: ; %entry
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_mov_b32_e32 v0, 0
+; GFX9-NEXT: ds_read_u16 v0, v0
+; GFX9-NEXT: v_mov_b32_e32 v1, 0x48ca
+; GFX9-NEXT: s_mov_b32 s4, 0
+; GFX9-NEXT: s_mov_b32 s5, 1
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: v_cmp_lt_i16_e32 vcc, v0, v1
+; GFX9-NEXT: s_cbranch_vccnz .LBB1_2
+; GFX9-NEXT: ; %bb.1: ; %LeafBlock1
+; GFX9-NEXT: v_cmp_ne_u16_e32 vcc, v0, v1
+; GFX9-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX9-NEXT: s_mov_b32 s5, 0
+; GFX9-NEXT: s_cselect_b32 s4, 1, 0
+; GFX9-NEXT: .LBB1_2: ; %Flow
+; GFX9-NEXT: s_xor_b32 s5, s5, 1
+; GFX9-NEXT: s_cmp_lg_u32 s5, 0
+; GFX9-NEXT: s_cbranch_scc1 .LBB1_4
+; GFX9-NEXT: ; %bb.3: ; %LeafBlock
+; GFX9-NEXT: v_mov_b32_e32 v1, 0x2524
+; GFX9-NEXT: v_cmp_ne_u16_e32 vcc, v0, v1
+; GFX9-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX9-NEXT: s_cselect_b32 s4, 1, 0
+; GFX9-NEXT: .LBB1_4: ; %Flow3
+; GFX9-NEXT: s_xor_b32 s5, s4, 1
+; GFX9-NEXT: s_mov_b32 s4, 0
+; GFX9-NEXT: s_cmp_lg_u32 s5, 0
+; GFX9-NEXT: s_cbranch_scc1 .LBB1_6
+; GFX9-NEXT: ; %bb.5: ; %SW_C2
+; GFX9-NEXT: v_mov_b32_e32 v1, 0x48ca
+; GFX9-NEXT: v_cmp_ne_u16_e32 vcc, v0, v1
+; GFX9-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX9-NEXT: s_cselect_b32 s4, 1, 0
+; GFX9-NEXT: .LBB1_6: ; %exit
+; GFX9-NEXT: s_xor_b32 s4, s4, 1
+; GFX9-NEXT: s_cmp_lg_u32 s4, 0
+; GFX9-NEXT: s_cbranch_scc1 .LBB1_8
+; GFX9-NEXT: ; %bb.7: ; %store
+; GFX9-NEXT: v_mov_b32_e32 v0, 0x63
+; GFX9-NEXT: v_mov_b32_e32 v1, 0
+; GFX9-NEXT: ds_write_b16 v1, v0
+; GFX9-NEXT: .LBB1_8: ; %end
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: vcc_s1_phi_switch:
+; GFX10: ; %bb.0: ; %entry
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_mov_b32_e32 v0, 0
+; GFX10-NEXT: s_mov_b32 s5, 0
+; GFX10-NEXT: s_mov_b32 s6, 1
+; GFX10-NEXT: ds_read_u16 v0, v0
+; GFX10-NEXT: s_waitcnt lgkmcnt(0)
+; GFX10-NEXT: v_cmp_ne_u16_e64 s4, 0x48ca, v0
+; GFX10-NEXT: v_cmp_gt_i16_e32 vcc_lo, 0x48ca, v0
+; GFX10-NEXT: s_cbranch_vccnz .LBB1_2
+; GFX10-NEXT: ; %bb.1: ; %LeafBlock1
+; GFX10-NEXT: s_cmp_lg_u32 s4, 0
+; GFX10-NEXT: s_mov_b32 s6, 0
+; GFX10-NEXT: s_cselect_b32 s5, 1, 0
+; GFX10-NEXT: .LBB1_2: ; %Flow
+; GFX10-NEXT: s_xor_b32 s6, s6, 1
+; GFX10-NEXT: s_cmp_lg_u32 s6, 0
+; GFX10-NEXT: s_cbranch_scc1 .LBB1_4
+; GFX10-NEXT: ; %bb.3: ; %LeafBlock
+; GFX10-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0x2524, v0
+; GFX10-NEXT: s_cmp_lg_u32 vcc_lo, 0
+; GFX10-NEXT: s_cselect_b32 s5, 1, 0
+; GFX10-NEXT: .LBB1_4: ; %Flow3
+; GFX10-NEXT: s_xor_b32 s6, s5, 1
+; GFX10-NEXT: s_mov_b32 s5, 0
+; GFX10-NEXT: s_cmp_lg_u32 s6, 0
+; GFX10-NEXT: s_cbranch_scc1 .LBB1_6
+; GFX10-NEXT: ; %bb.5: ; %SW_C2
+; GFX10-NEXT: s_cmp_lg_u32 s4, 0
+; GFX10-NEXT: s_cselect_b32 s5, 1, 0
+; GFX10-NEXT: .LBB1_6: ; %exit
+; GFX10-NEXT: s_xor_b32 s4, s5, 1
+; GFX10-NEXT: s_cmp_lg_u32 s4, 0
+; GFX10-NEXT: s_cbranch_scc1 .LBB1_8
+; GFX10-NEXT: ; %bb.7: ; %store
+; GFX10-NEXT: v_mov_b32_e32 v0, 0x63
+; GFX10-NEXT: v_mov_b32_e32 v1, 0
+; GFX10-NEXT: ds_write_b16 v1, v0
+; GFX10-NEXT: .LBB1_8: ; %end
+; GFX10-NEXT: s_waitcnt lgkmcnt(0)
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %ld = load i16, ptr addrspace(3) null, align 2
+ switch i16 %ld, label %SW_C2 [
+ i16 9508, label %exit
+ i16 18634, label %exit
+ ]
+
+SW_C2:
+ %cmp = icmp ne i16 %ld, 18634
+ br label %exit
+
+exit:
+ %phi = phi i1 [ false, %entry ], [ false, %entry ], [ %cmp, %SW_C2 ]
+ br i1 %phi, label %store, label %end
+
+store:
+ store i16 99, ptr addrspace(3) null, align 2
+ br label %end
+
+end:
+ ret void
+}
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