[llvm] [AArch64] Refine reduction VT selection in CTPOP -> VECREDUCE combine (PR #183025)

[Paul Walker via llvm-commits]

================
@@ -29223,14 +29225,24 @@ static SDValue performCTPOPCombine(SDNode *N,
       MaskVT.getVectorElementType() != MVT::i1)
     return SDValue();
 
-  EVT ReduceInVT =
-      EVT::getVectorVT(*DAG.getContext(), VT, MaskVT.getVectorElementCount());
+  EVT ReduceInVT = EVT::getVectorVT(*DAG.getContext(), SrcVT,
+                                    MaskVT.getVectorElementCount());
+
+  EVT CmpVT;
+  // Use the same VT as the SETcc if -CTPOP would not overflow.
+  if (sd_match(Mask, m_SetCC(m_VT(CmpVT), m_Value(), m_Value()))) {
+    CmpVT = CmpVT.changeVectorElementTypeToInteger();
+    if (MaskVT.getSizeInBits() <= (1 << (CmpVT.getScalarSizeInBits() - 1)))
----------------
paulwalker-arm wrote:

```suggestion
    if (CmpVT.getScalarSizeInBits() > llvm::Log2_64_Ceil(MaskVT.getSizeInBits()))
```
because `1 << ?` is not going to work for vectors of i128 elements.

https://github.com/llvm/llvm-project/pull/183025