[llvm] [RISCV] Remove RISCVVectorPeephole::tryToReduceVL (PR #184297)
Luke Lau via llvm-commits
llvm-commits at lists.llvm.org
Wed Mar 4 05:57:24 PST 2026
https://github.com/lukel97 updated https://github.com/llvm/llvm-project/pull/184297
>From 1d8b1f0d015f684ddb884a7098a0f7acf78c7f35 Mon Sep 17 00:00:00 2001
From: Luke Lau <luke at igalia.com>
Date: Tue, 3 Mar 2026 15:39:07 +0800
Subject: [PATCH] [RISCV] Remove RISCVVectorPeephole::tryToReduceVL
Stacked on #184155
Now that RISCVVLOptimizer has been extended to handle the remaining cases tryToReduceVL handles, we can remove tryToReduceVL to keep all the reduction logic in one place.
Intended to be NFC but it looks like in test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector-shuffle.ll we were previously reducing the vl of a volatile load in insert_subvector_dag_loop, which this RISCVVLOptimizer knows to avoid.
On llvm-test-suite and SPEC CPU 2017 -march=rva23u64 -O3 there are no changes with this patch.
---
llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp | 106 +-----------------
.../fixed-vectors-insert-subvector-shuffle.ll | 3 +-
.../CodeGen/RISCV/rvv/reduce-vl-peephole.ll | 19 ----
.../CodeGen/RISCV/rvv/reduce-vl-peephole.mir | 15 ---
.../RISCV/rvv/rvv-peephole-vmerge-to-vmv.mir | 4 +-
.../CodeGen/RISCV/rvv/vmv.v.v-peephole.mir | 6 +-
6 files changed, 8 insertions(+), 145 deletions(-)
delete mode 100644 llvm/test/CodeGen/RISCV/rvv/reduce-vl-peephole.ll
delete mode 100644 llvm/test/CodeGen/RISCV/rvv/reduce-vl-peephole.mir
diff --git a/llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp b/llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
index 07110c4b7f1ad..6fc2274b026e8 100644
--- a/llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
+++ b/llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
@@ -59,7 +59,6 @@ class RISCVVectorPeephole : public MachineFunctionPass {
}
private:
- bool tryToReduceVL(MachineInstr &MI) const;
bool convertToVLMAX(MachineInstr &MI) const;
bool convertToWholeRegister(MachineInstr &MI) const;
bool convertToUnmasked(MachineInstr &MI) const;
@@ -98,106 +97,6 @@ bool RISCVVectorPeephole::hasSameEEW(const MachineInstr &User,
return SrcLog2EEW == UserLog2SEW;
}
-// Attempt to reduce the VL of an instruction whose sole use is feeding a
-// instruction with a narrower VL. This currently works backwards from the
-// user instruction (which might have a smaller VL).
-bool RISCVVectorPeephole::tryToReduceVL(MachineInstr &MI) const {
- // Note that the goal here is a bit multifaceted.
- // 1) For store's reducing the VL of the value being stored may help to
- // reduce VL toggles. This is somewhat of an artifact of the fact we
- // promote arithmetic instructions but VL predicate stores.
- // 2) For vmv.v.v reducing VL eagerly on the source instruction allows us
- // to share code with the foldVMV_V_V transform below.
- //
- // Note that to the best of our knowledge, reducing VL is generally not
- // a significant win on real hardware unless we can also reduce LMUL which
- // this code doesn't try to do.
- //
- // TODO: We can handle a bunch more instructions here, and probably
- // recurse backwards through operands too.
- SmallVector<unsigned, 2> SrcIndices = {0};
- switch (RISCV::getRVVMCOpcode(MI.getOpcode())) {
- default:
- return false;
- case RISCV::VSE8_V:
- case RISCV::VSE16_V:
- case RISCV::VSE32_V:
- case RISCV::VSE64_V:
- break;
- case RISCV::VMV_V_V:
- SrcIndices[0] = 2;
- break;
- case RISCV::VMERGE_VVM:
- SrcIndices.assign({2, 3});
- break;
- case RISCV::VREDSUM_VS:
- case RISCV::VREDMAXU_VS:
- case RISCV::VREDMAX_VS:
- case RISCV::VREDMINU_VS:
- case RISCV::VREDMIN_VS:
- case RISCV::VREDAND_VS:
- case RISCV::VREDOR_VS:
- case RISCV::VREDXOR_VS:
- case RISCV::VWREDSUM_VS:
- case RISCV::VWREDSUMU_VS:
- case RISCV::VFREDUSUM_VS:
- case RISCV::VFREDOSUM_VS:
- case RISCV::VFREDMAX_VS:
- case RISCV::VFREDMIN_VS:
- case RISCV::VFWREDUSUM_VS:
- case RISCV::VFWREDOSUM_VS:
- SrcIndices[0] = 2;
- break;
- }
-
- MachineOperand &VL = MI.getOperand(RISCVII::getVLOpNum(MI.getDesc()));
- if (VL.isImm() && VL.getImm() == RISCV::VLMaxSentinel)
- return false;
-
- bool Changed = false;
- for (unsigned SrcIdx : SrcIndices) {
- Register SrcReg = MI.getOperand(SrcIdx).getReg();
- // Note: one *use*, not one *user*.
- if (!MRI->hasOneUse(SrcReg))
- continue;
-
- MachineInstr *Src = MRI->getVRegDef(SrcReg);
- if (!Src || Src->hasUnmodeledSideEffects() ||
- Src->getParent() != MI.getParent() || Src->getNumDefs() != 1 ||
- !RISCVII::hasVLOp(Src->getDesc().TSFlags) ||
- !RISCVII::hasSEWOp(Src->getDesc().TSFlags))
- continue;
-
- // Src's dest needs to have the same EEW as MI's input.
- if (!hasSameEEW(MI, *Src))
- continue;
-
- bool ElementsDependOnVL = RISCVII::elementsDependOnVL(
- TII->get(RISCV::getRVVMCOpcode(Src->getOpcode())).TSFlags);
- if (ElementsDependOnVL || Src->mayRaiseFPException())
- continue;
-
- MachineOperand &SrcVL =
- Src->getOperand(RISCVII::getVLOpNum(Src->getDesc()));
- if (VL.isIdenticalTo(SrcVL) || !RISCV::isVLKnownLE(VL, SrcVL))
- continue;
-
- if (!ensureDominates(VL, *Src))
- continue;
-
- if (VL.isImm())
- SrcVL.ChangeToImmediate(VL.getImm());
- else if (VL.isReg())
- SrcVL.ChangeToRegister(VL.getReg(), false);
-
- Changed = true;
- }
-
- // TODO: For instructions with a passthru, we could clear the passthru
- // and tail policy since we've just proven the tail is not demanded.
- return Changed;
-}
-
/// Check if an operand is an immediate or a materialized ADDI $x0, imm.
std::optional<unsigned>
RISCVVectorPeephole::getConstant(const MachineOperand &VL) const {
@@ -603,7 +502,7 @@ bool RISCVVectorPeephole::foldUndefPassthruVMV_V_V(MachineInstr &MI) {
///
/// %x = PseudoVADD_V_V_M1 %passthru, %a, %b, %vl1, sew, policy
/// %y = PseudoVMV_V_V_M1 %passthru, %x, %vl2, sew, policy
-/// (where %vl1 <= %vl2, see related tryToReduceVL)
+/// (where %vl1 <= %vl2)
///
/// ->
///
@@ -646,7 +545,7 @@ bool RISCVVectorPeephole::foldVMV_V_V(MachineInstr &MI) {
NeedsCommute = {OpIdx1, OpIdx2};
}
- // Src VL will have already been reduced if legal (see tryToReduceVL),
+ // Src VL will have already been reduced if legal by RISCVVLOptimizer,
// so we don't need to handle a smaller source VL here. However, the
// user's VL may be larger
MachineOperand &SrcVL = Src->getOperand(RISCVII::getVLOpNum(Src->getDesc()));
@@ -880,7 +779,6 @@ bool RISCVVectorPeephole::runOnMachineFunction(MachineFunction &MF) {
for (MachineInstr &MI : make_early_inc_range(MBB)) {
Changed |= convertToVLMAX(MI);
- Changed |= tryToReduceVL(MI);
Changed |= convertToUnmasked(MI);
Changed |= convertToWholeRegister(MI);
Changed |= convertAllOnesVMergeToVMv(MI);
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector-shuffle.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector-shuffle.ll
index 8efb48a8cb691..94bec7c43c0a2 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector-shuffle.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector-shuffle.ll
@@ -190,9 +190,8 @@ define <4 x i32> @insert_subvector_vp_add_v4i32_v8i32(<4 x i32> %v1, <8 x i32> %
define <4 x i32> @insert_subvector_dag_loop(ptr %p, ptr %q) {
; CHECK-LABEL: insert_subvector_dag_loop:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 2, e32, m1, ta, ma
-; CHECK-NEXT: vle32.v v9, (a0)
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; CHECK-NEXT: vle32.v v9, (a0)
; CHECK-NEXT: vle32.v v8, (a1)
; CHECK-NEXT: vsetivli zero, 2, e32, m1, tu, ma
; CHECK-NEXT: vmv.v.v v8, v9
diff --git a/llvm/test/CodeGen/RISCV/rvv/reduce-vl-peephole.ll b/llvm/test/CodeGen/RISCV/rvv/reduce-vl-peephole.ll
deleted file mode 100644
index 7f70b0ed224ec..0000000000000
--- a/llvm/test/CodeGen/RISCV/rvv/reduce-vl-peephole.ll
+++ /dev/null
@@ -1,19 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc < %s -mtriple=riscv64 -mattr=+v -verify-machineinstrs | FileCheck %s
-
-define void @avl_not_dominated(<vscale x 2 x i32> %v, ptr %p) {
-; CHECK-LABEL: avl_not_dominated:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; CHECK-NEXT: vmv.x.s a1, v8
-; CHECK-NEXT: slli a1, a1, 32
-; CHECK-NEXT: srli a1, a1, 32
-; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
-; CHECK-NEXT: vadd.vi v8, v8, 1
-; CHECK-NEXT: vse32.v v8, (a0)
-; CHECK-NEXT: ret
- %w = add <vscale x 2 x i32> %v, splat (i32 1)
- %evl = extractelement <vscale x 2 x i32> %v, i32 0
- call void @llvm.vp.store(<vscale x 2 x i32> %w, ptr %p, <vscale x 2 x i1> splat(i1 true), i32 %evl)
- ret void
-}
diff --git a/llvm/test/CodeGen/RISCV/rvv/reduce-vl-peephole.mir b/llvm/test/CodeGen/RISCV/rvv/reduce-vl-peephole.mir
deleted file mode 100644
index a17c88040cdf4..0000000000000
--- a/llvm/test/CodeGen/RISCV/rvv/reduce-vl-peephole.mir
+++ /dev/null
@@ -1,15 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
-# RUN: llc %s -o - -mtriple=riscv64 -mattr=+v -run-pass=riscv-vector-peephole \
-# RUN: -verify-machineinstrs | FileCheck %s
----
-name: avl_not_dominated
-body: |
- bb.0:
- ; CHECK-LABEL: name: avl_not_dominated
- ; CHECK: %evl:gprnox0 = ADDI $x0, 1
- ; CHECK-NEXT: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, %evl /* vl */, 5 /* e32 */, 0 /* tu, mu */
- ; CHECK-NEXT: PseudoVSE32_V_M1 %x, $noreg, %evl /* vl */, 5 /* e32 */
- %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 5 /* e32 */, 0 /* tu, mu */
- %evl:gprnox0 = ADDI $x0, 1
- PseudoVSE32_V_M1 %x:vr, $noreg, %evl, 5 /* e32 */
-...
diff --git a/llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-to-vmv.mir b/llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-to-vmv.mir
index 4cd46a1b7d22a..cc1229ed96c91 100644
--- a/llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-to-vmv.mir
+++ b/llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-to-vmv.mir
@@ -77,7 +77,7 @@ body: |
; CHECK-NEXT: %pt:vr = COPY $v8
; CHECK-NEXT: %false:vrnov0 = COPY $v9
; CHECK-NEXT: %mask:vmv0 = COPY $v0
- ; CHECK-NEXT: %true:vrnov0 = PseudoVADD_VV_M1_MASK %false, $noreg, $noreg, %mask, 4 /* vl */, 5 /* e32 */, 0 /* tu, mu */
+ ; CHECK-NEXT: %true:vrnov0 = PseudoVADD_VV_M1_MASK %false, $noreg, $noreg, %mask, 8 /* vl */, 5 /* e32 */, 0 /* tu, mu */
; CHECK-NEXT: %x:vr = PseudoVMV_V_V_M1 %pt, %true, 4 /* vl */, 5 /* e32 */, 0 /* tu, mu */
%pt:vrnov0 = COPY $v8
%false:vrnov0 = COPY $v9
@@ -200,7 +200,7 @@ body: |
; CHECK-NEXT: %pt:vr = COPY $v8
; CHECK-NEXT: %false:vrnov0 = COPY $v9
; CHECK-NEXT: %mask:vmv0 = COPY $v0
- ; CHECK-NEXT: %true:vrnov0 = PseudoVADD_VV_M1_MASK %false, $noreg, $noreg, %mask, 1 /* vl */, 5 /* e32 */, 3 /* ta, ma */
+ ; CHECK-NEXT: %true:vrnov0 = PseudoVADD_VV_M1_MASK %false, $noreg, $noreg, %mask, 2 /* vl */, 5 /* e32 */, 3 /* ta, ma */
; CHECK-NEXT: [[PseudoVMV_V_V_M1_:%[0-9]+]]:vr = PseudoVMV_V_V_M1 %pt, %true, 1 /* vl */, 5 /* e32 */, 0 /* tu, mu */
%pt:vrnov0 = COPY $v8
%false:vrnov0 = COPY $v9
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.mir b/llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.mir
index 61dd49a42fffa..50c87eda56092 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.mir
+++ b/llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.mir
@@ -115,7 +115,7 @@ body: |
; CHECK-NEXT: [[PseudoVMV_V_I_MF2_:%[0-9]+]]:vrnov0 = PseudoVMV_V_I_MF2 $noreg, 0, 0 /* vl */, 5 /* e32 */, 1 /* ta, mu */
; CHECK-NEXT: [[COPY:%[0-9]+]]:vmv0 = COPY $v8
; CHECK-NEXT: [[PseudoVADD_VV_M1_MASK:%[0-9]+]]:vrnov0 = PseudoVADD_VV_M1_MASK [[PseudoVMV_V_I_MF2_]], $noreg, $noreg, [[COPY]], 0 /* vl */, 5 /* e32 */, 0 /* tu, mu */
- %0:vr = PseudoVMV_V_I_MF2 $noreg, 0, -1, 5 /* e32 */, 0 /* tu, mu */
+ %0:vr = PseudoVMV_V_I_MF2 $noreg, 0, 0, 5 /* e32 */, 0 /* tu, mu */
%1:vrnov0 = PseudoVMV_V_V_MF2 $noreg, %0, 0, 5 /* e32 */, 0 /* tu, mu */
%2:vmv0 = COPY $v8
%3:vrnov0 = PseudoVADD_VV_M1_MASK %1, $noreg, $noreg, %2, 0, 5 /* e32 */, 0 /* tu, mu */
@@ -131,7 +131,7 @@ body: |
; CHECK-NEXT: [[PseudoVMV_V_I_MF2_:%[0-9]+]]:vrnov0 = PseudoVMV_V_I_MF2 $noreg, 0, 0 /* vl */, 5 /* e32 */, 1 /* ta, mu */
; CHECK-NEXT: [[COPY:%[0-9]+]]:vmv0 = COPY $v8
; CHECK-NEXT: [[PseudoVLSE32_V_MF2_MASK:%[0-9]+]]:vrnov0 = PseudoVLSE32_V_MF2_MASK [[PseudoVMV_V_I_MF2_]], $noreg, $noreg, [[COPY]], 0 /* vl */, 5 /* e32 */, 0 /* tu, mu */ :: (load unknown-size, align 4)
- %2:vr = PseudoVMV_V_I_MF2 $noreg, 0, -1, 5 /* e32 */, 0 /* tu, mu */
+ %2:vr = PseudoVMV_V_I_MF2 $noreg, 0, 0, 5 /* e32 */, 0 /* tu, mu */
%3:vrnov0 = PseudoVMV_V_V_MF2 $noreg, %2, 0, 5 /* e32 */, 0 /* tu, mu */
%7:vmv0 = COPY $v8
%6:vrnov0 = PseudoVLSE32_V_MF2_MASK %3, $noreg, $noreg, %7, 0, 5 /* e32 */, 0 /* tu, mu */ :: (load unknown-size, align 4)
@@ -185,6 +185,6 @@ body: |
%passthru:vrnov0 = COPY $v8
%x:vr = COPY $v9
%y:vr = COPY $v10
- %vfmadd:vrnov0 = nofpexcept PseudoVFMADD_VV_M1_E32 %x, %y, %passthru, 7, -1, 5 /* e32 */, 3 /* ta, ma */, implicit $frm
+ %vfmadd:vrnov0 = nofpexcept PseudoVFMADD_VV_M1_E32 %x, %y, %passthru, 7, %avl, 5 /* e32 */, 3 /* ta, ma */, implicit $frm
%vmerge:vrnov0 = PseudoVMV_V_V_M1 %passthru, %vfmadd, %avl, 5 /* e32 */, 0 /* tu, mu */
...
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