[llvm] [NFC][SPIRV] Rename `selectSelectDefaultArgs` to `selectExtendBool` (PR #184120)
Juan Manuel Martinez Caamaño via llvm-commits
llvm-commits at lists.llvm.org
Wed Mar 4 05:02:19 PST 2026
https://github.com/jmmartinez updated https://github.com/llvm/llvm-project/pull/184120
>From 72ef0a79584439272bc71dfdc7cc8f500a458081 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Juan=20Manuel=20Martinez=20Caama=C3=B1o?=
<jmartinezcaamao at gmail.com>
Date: Mon, 2 Mar 2026 14:36:33 +0100
Subject: [PATCH 1/2] [NFC][SPIRV] Rename `selectSelectDefaultArgs` to
`selectExtendBool`
---
.../Target/SPIRV/SPIRVInstructionSelector.cpp | 18 ++++++++++--------
1 file changed, 10 insertions(+), 8 deletions(-)
diff --git a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
index 344628f258229..d2ca98f054a5d 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
@@ -266,8 +266,8 @@ class SPIRVInstructionSelector : public InstructionSelector {
bool selectSelect(Register ResVReg, SPIRVTypeInst ResType,
MachineInstr &I) const;
- bool selectSelectDefaultArgs(Register ResVReg, SPIRVTypeInst ResType,
- MachineInstr &I, bool IsSigned) const;
+ bool selectExtendBool(Register ResVReg, SPIRVTypeInst ResType,
+ MachineInstr &I, bool IsSigned) const;
bool selectIToF(Register ResVReg, SPIRVTypeInst ResType, MachineInstr &I,
bool IsSigned, unsigned Opcode) const;
bool selectExt(Register ResVReg, SPIRVTypeInst ResType, MachineInstr &I,
@@ -3382,10 +3382,12 @@ bool SPIRVInstructionSelector::selectSelect(Register ResVReg,
return true;
}
-bool SPIRVInstructionSelector::selectSelectDefaultArgs(Register ResVReg,
- SPIRVTypeInst ResType,
- MachineInstr &I,
- bool IsSigned) const {
+// This function is used to extend a bool or a vector of bools into an integer
+// or vector of integers.
+bool SPIRVInstructionSelector::selectExtendBool(Register ResVReg,
+ SPIRVTypeInst ResType,
+ MachineInstr &I,
+ bool IsSigned) const {
// To extend a bool, we need to use OpSelect between constants.
Register ZeroReg = buildZerosVal(ResType, I);
Register OneReg = buildOnesVal(IsSigned, ResType, I);
@@ -3418,7 +3420,7 @@ bool SPIRVInstructionSelector::selectIToF(Register ResVReg,
TmpType = GR.getOrCreateSPIRVVectorType(TmpType, NumElts, I, TII);
}
SrcReg = createVirtualRegister(TmpType, &GR, MRI, MRI->getMF());
- selectSelectDefaultArgs(SrcReg, TmpType, I, false);
+ selectExtendBool(SrcReg, TmpType, I, false);
}
return selectOpWithSrcs(ResVReg, ResType, I, {SrcReg}, Opcode);
}
@@ -3428,7 +3430,7 @@ bool SPIRVInstructionSelector::selectExt(Register ResVReg,
bool IsSigned) const {
Register SrcReg = I.getOperand(1).getReg();
if (GR.isScalarOrVectorOfType(SrcReg, SPIRV::OpTypeBool))
- return selectSelectDefaultArgs(ResVReg, ResType, I, IsSigned);
+ return selectExtendBool(ResVReg, ResType, I, IsSigned);
SPIRVTypeInst SrcType = GR.getSPIRVTypeForVReg(SrcReg);
if (ResType == SrcType)
>From 697054da835d64d7da292be6f5b11589b7384df8 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Juan=20Manuel=20Martinez=20Caama=C3=B1o?=
<jmartinezcaamao at gmail.com>
Date: Wed, 4 Mar 2026 14:01:17 +0100
Subject: [PATCH 2/2] Review
---
.../Target/SPIRV/SPIRVInstructionSelector.cpp | 31 ++++++++++---------
1 file changed, 17 insertions(+), 14 deletions(-)
diff --git a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
index d2ca98f054a5d..dd0830bb879f5 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
@@ -266,8 +266,9 @@ class SPIRVInstructionSelector : public InstructionSelector {
bool selectSelect(Register ResVReg, SPIRVTypeInst ResType,
MachineInstr &I) const;
- bool selectExtendBool(Register ResVReg, SPIRVTypeInst ResType,
- MachineInstr &I, bool IsSigned) const;
+ bool selectBoolToInt(Register ResVReg, SPIRVTypeInst ResType,
+ Register BooleanVReg, MachineInstr &InsertAt,
+ bool IsSigned) const;
bool selectIToF(Register ResVReg, SPIRVTypeInst ResType, MachineInstr &I,
bool IsSigned, unsigned Opcode) const;
bool selectExt(Register ResVReg, SPIRVTypeInst ResType, MachineInstr &I,
@@ -3384,21 +3385,22 @@ bool SPIRVInstructionSelector::selectSelect(Register ResVReg,
// This function is used to extend a bool or a vector of bools into an integer
// or vector of integers.
-bool SPIRVInstructionSelector::selectExtendBool(Register ResVReg,
- SPIRVTypeInst ResType,
- MachineInstr &I,
- bool IsSigned) const {
+bool SPIRVInstructionSelector::selectBoolToInt(Register ResVReg,
+ SPIRVTypeInst ResType,
+ Register BooleanVReg,
+ MachineInstr &InsertAt,
+ bool IsSigned) const {
// To extend a bool, we need to use OpSelect between constants.
- Register ZeroReg = buildZerosVal(ResType, I);
- Register OneReg = buildOnesVal(IsSigned, ResType, I);
- bool IsScalarBool =
- GR.isScalarOfType(I.getOperand(1).getReg(), SPIRV::OpTypeBool);
+ Register ZeroReg = buildZerosVal(ResType, InsertAt);
+ Register OneReg = buildOnesVal(IsSigned, ResType, InsertAt);
+ bool IsScalarBool = GR.isScalarOfType(BooleanVReg, SPIRV::OpTypeBool);
unsigned Opcode =
IsScalarBool ? SPIRV::OpSelectSISCond : SPIRV::OpSelectVIVCond;
- BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Opcode))
+ BuildMI(*InsertAt.getParent(), InsertAt, InsertAt.getDebugLoc(),
+ TII.get(Opcode))
.addDef(ResVReg)
.addUse(GR.getSPIRVTypeID(ResType))
- .addUse(I.getOperand(1).getReg())
+ .addUse(BooleanVReg)
.addUse(OneReg)
.addUse(ZeroReg)
.constrainAllUses(TII, TRI, RBI);
@@ -3420,7 +3422,7 @@ bool SPIRVInstructionSelector::selectIToF(Register ResVReg,
TmpType = GR.getOrCreateSPIRVVectorType(TmpType, NumElts, I, TII);
}
SrcReg = createVirtualRegister(TmpType, &GR, MRI, MRI->getMF());
- selectExtendBool(SrcReg, TmpType, I, false);
+ selectBoolToInt(SrcReg, TmpType, I.getOperand(1).getReg(), I, false);
}
return selectOpWithSrcs(ResVReg, ResType, I, {SrcReg}, Opcode);
}
@@ -3430,7 +3432,8 @@ bool SPIRVInstructionSelector::selectExt(Register ResVReg,
bool IsSigned) const {
Register SrcReg = I.getOperand(1).getReg();
if (GR.isScalarOrVectorOfType(SrcReg, SPIRV::OpTypeBool))
- return selectExtendBool(ResVReg, ResType, I, IsSigned);
+ return selectBoolToInt(ResVReg, ResType, I.getOperand(1).getReg(), I,
+ IsSigned);
SPIRVTypeInst SrcType = GR.getSPIRVTypeForVReg(SrcReg);
if (ResType == SrcType)
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