[llvm] 177211a - [AArch64] Generate test checks (NFC) (#184582)
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Wed Mar 4 02:36:09 PST 2026
Author: Nikita Popov
Date: 2026-03-04T11:36:04+01:00
New Revision: 177211a99f70d21fb73e1417d51cf86b1d1e4dd5
URL: https://github.com/llvm/llvm-project/commit/177211a99f70d21fb73e1417d51cf86b1d1e4dd5
DIFF: https://github.com/llvm/llvm-project/commit/177211a99f70d21fb73e1417d51cf86b1d1e4dd5.diff
LOG: [AArch64] Generate test checks (NFC) (#184582)
Added:
Modified:
llvm/test/CodeGen/AArch64/arm64-fmax-safe.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AArch64/arm64-fmax-safe.ll b/llvm/test/CodeGen/AArch64/arm64-fmax-safe.ll
index aec31eced397e..159075db0f7bc 100644
--- a/llvm/test/CodeGen/AArch64/arm64-fmax-safe.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-fmax-safe.ll
@@ -1,54 +1,70 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc < %s -mtriple=arm64-eabi | FileCheck %s
define double @test_direct(float %in) {
; CHECK-LABEL: test_direct:
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi d1, #0000000000000000
+; CHECK-NEXT: fcmp s0, #0.0
+; CHECK-NEXT: fcsel s0, s1, s0, mi
+; CHECK-NEXT: fcvt d0, s0
+; CHECK-NEXT: ret
%cmp = fcmp olt float %in, 0.000000e+00
%val = select i1 %cmp, float 0.000000e+00, float %in
%longer = fpext float %val to double
ret double %longer
-; CHECK: fcmp
-; CHECK: fcsel
}
define double @test_cross(float %in) {
; CHECK-LABEL: test_cross:
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi d1, #0000000000000000
+; CHECK-NEXT: fcmp s0, #0.0
+; CHECK-NEXT: fcsel s0, s0, s1, lt
+; CHECK-NEXT: fcvt d0, s0
+; CHECK-NEXT: ret
%cmp = fcmp ult float %in, 0.000000e+00
%val = select i1 %cmp, float %in, float 0.000000e+00
%longer = fpext float %val to double
ret double %longer
-
-; CHECK: fcmp
-; CHECK: fcsel
}
; Same as previous, but with ordered comparison;
; must become fminnm, not fmin.
define double @test_cross_fail_nan(float %in) {
; CHECK-LABEL: test_cross_fail_nan:
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi d1, #0000000000000000
+; CHECK-NEXT: fminnm s0, s0, s1
+; CHECK-NEXT: fcvt d0, s0
+; CHECK-NEXT: ret
%cmp = fcmp olt float %in, 0.000000e+00
%val = select i1 %cmp, float %in, float 0.000000e+00
%longer = fpext float %val to double
ret double %longer
-
-; CHECK: fminnm s
}
; This isn't a min or a max, but passes the first condition for swapping the
; results. Make sure they're put back before we resort to the normal fcsel.
define float @test_cross_fail(float %lhs, float %rhs) {
; CHECK-LABEL: test_cross_fail:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcmp s0, s1
+; CHECK-NEXT: fcsel s0, s1, s0, ne
+; CHECK-NEXT: ret
%tst = fcmp une float %lhs, %rhs
%res = select i1 %tst, float %rhs, float %lhs
ret float %res
-
- ; The register allocator would have to decide to be deliberately obtuse before
- ; other register were used.
-; CHECK: fcsel s0, s1, s0, ne
}
; Make sure the transformation isn't triggered for integers
define i64 @test_integer(i64 %in) {
+; CHECK-LABEL: test_integer:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmp x0, #0
+; CHECK-NEXT: csel x0, xzr, x0, mi
+; CHECK-NEXT: ret
%cmp = icmp slt i64 %in, 0
%val = select i1 %cmp, i64 0, i64 %in
ret i64 %val
@@ -57,18 +73,22 @@ define i64 @test_integer(i64 %in) {
; Make sure we don't translate it into fminnm when the nsz flag is set on the fcmp.
define float @minnum_fcmp_nsz(float %x, float %y) {
; CHECK-LABEL: minnum_fcmp_nsz:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcmp s0, s1
+; CHECK-NEXT: fcsel s0, s0, s1, le
+; CHECK-NEXT: ret
%cmp = fcmp nnan nsz ole float %x, %y
%sel = select i1 %cmp, float %x, float %y
ret float %sel
-; CHECK-NOT: fminnm
-; CHECK: fcsel s0, s0, s1, le
}
; Make sure we translate it into fminnm when the nsz flag is set on the select.
define float @minnum_select_nsz(float %x, float %y) {
; CHECK-LABEL: minnum_select_nsz:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fminnm s0, s0, s1
+; CHECK-NEXT: ret
%cmp = fcmp nnan ole float %x, %y
%sel = select nsz i1 %cmp, float %x, float %y
ret float %sel
-; CHECK: fminnm s0, s0, s1
}
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