[llvm] [SPIR-V] Complete SPV_INTEL_16bit_atomics extension support (PR #184312)

[Viktoria Maximova via llvm-commits]

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@@ -1622,10 +1622,44 @@ void addInstrRequirements(const MachineInstr &MI,
     assert(InstrPtr->getOperand(1).isReg() && "Unexpected operand in atomic");
     Register TypeReg = InstrPtr->getOperand(1).getReg();
     SPIRVTypeInst TypeDef = MRI.getVRegDef(TypeReg);
+    unsigned Op = MI.getOpcode();
+
     if (TypeDef->getOpcode() == SPIRV::OpTypeInt) {
       unsigned BitWidth = TypeDef->getOperand(1).getImm();
       if (BitWidth == 64)
         Reqs.addCapability(SPIRV::Capability::Int64Atomics);
+      else if (BitWidth == 16) {
+        if (!ST.canUseExtension(SPIRV::Extension::SPV_INTEL_16bit_atomics))
+          report_fatal_error(
+              "16-bit integer atomic operations require the following SPIR-V "
+              "extension: SPV_INTEL_16bit_atomics",
+              false);
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vmaksimo wrote:

These rules are in the client API environment specs.  See:
https://registry.khronos.org/OpenCL/specs/3.0-unified/html/OpenCL_Env.html#validation-rules:

> For all Atomic Instructions:
    Only 32-bit integer types are supported for the Result Type and/or type of Value.

There are additional rules for floating-point types added by the float atomic extension, similar to the additional rules for 16-bit types in [16-bit atomic extension](https://github.com/intel/llvm/blob/sycl/sycl/doc/design/spirv-extensions/SPV_INTEL_16bit_atomics.asciidoc):
> This extension extends the atomic support in SPIR-V to support atomic operations on 16-bit integer in memory

https://github.com/llvm/llvm-project/pull/184312