[llvm] [ARM] Generate test checks (NFC) (PR #184574)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Mar 4 01:37:27 PST 2026
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-arm
Author: Nikita Popov (nikic)
<details>
<summary>Changes</summary>
I had to rename some functions to make them UTC compatible.
---
Patch is 30.97 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/184574.diff
1 Files Affected:
- (modified) llvm/test/CodeGen/ARM/vminmaxnm-safe.ll (+536-132)
``````````diff
diff --git a/llvm/test/CodeGen/ARM/vminmaxnm-safe.ll b/llvm/test/CodeGen/ARM/vminmaxnm-safe.ll
index 5577ab49bb830..9d0fef6452a38 100644
--- a/llvm/test/CodeGen/ARM/vminmaxnm-safe.ll
+++ b/llvm/test/CodeGen/ARM/vminmaxnm-safe.ll
@@ -1,10 +1,17 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc < %s -mtriple armv8 -mattr=+neon,+fp-armv8 | FileCheck %s
; vectors
define <4 x float> @vmaxnmq(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vmaxnmq:
-; CHECK: vmaxnm.f32 q{{[0-9]+}}, q{{[0-9]+}}, q{{[0-9]+}}
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
+; CHECK-NEXT: vld1.64 {d18, d19}, [r0]
+; CHECK-NEXT: vmaxnm.f32 q8, q9, q8
+; CHECK-NEXT: vmov r0, r1, d16
+; CHECK-NEXT: vmov r2, r3, d17
+; CHECK-NEXT: bx lr
%tmp1 = load <4 x float>, ptr %A
%tmp2 = load <4 x float>, ptr %B
%tmp3 = call <4 x float> @llvm.arm.neon.vmaxnm.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
@@ -13,7 +20,12 @@ define <4 x float> @vmaxnmq(ptr %A, ptr %B) nounwind {
define <2 x float> @vmaxnmd(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vmaxnmd:
-; CHECK: vmaxnm.f32 d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vldr d16, [r1]
+; CHECK-NEXT: vldr d17, [r0]
+; CHECK-NEXT: vmaxnm.f32 d16, d17, d16
+; CHECK-NEXT: vmov r0, r1, d16
+; CHECK-NEXT: bx lr
%tmp1 = load <2 x float>, ptr %A
%tmp2 = load <2 x float>, ptr %B
%tmp3 = call <2 x float> @llvm.arm.neon.vmaxnm.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
@@ -22,7 +34,13 @@ define <2 x float> @vmaxnmd(ptr %A, ptr %B) nounwind {
define <4 x float> @vminnmq(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vminnmq:
-; CHECK: vminnm.f32 q{{[0-9]+}}, q{{[0-9]+}}, q{{[0-9]+}}
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
+; CHECK-NEXT: vld1.64 {d18, d19}, [r0]
+; CHECK-NEXT: vminnm.f32 q8, q9, q8
+; CHECK-NEXT: vmov r0, r1, d16
+; CHECK-NEXT: vmov r2, r3, d17
+; CHECK-NEXT: bx lr
%tmp1 = load <4 x float>, ptr %A
%tmp2 = load <4 x float>, ptr %B
%tmp3 = call <4 x float> @llvm.arm.neon.vminnm.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
@@ -31,7 +49,12 @@ define <4 x float> @vminnmq(ptr %A, ptr %B) nounwind {
define <2 x float> @vminnmd(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: vminnmd:
-; CHECK: vminnm.f32 d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vldr d16, [r1]
+; CHECK-NEXT: vldr d17, [r0]
+; CHECK-NEXT: vminnm.f32 d16, d17, d16
+; CHECK-NEXT: vmov r0, r1, d16
+; CHECK-NEXT: bx lr
%tmp1 = load <2 x float>, ptr %A
%tmp2 = load <2 x float>, ptr %B
%tmp3 = call <2 x float> @llvm.arm.neon.vminnm.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
@@ -40,129 +63,241 @@ define <2 x float> @vminnmd(ptr %A, ptr %B) nounwind {
; scalars
-define float @fp-armv8_vminnm_o(float %a, float %b) {
-; CHECK-LABEL: "fp-armv8_vminnm_o":
-; CHECK-NOT: vminnm.f32
+define float @fp_armv8_vminnm_o(float %a, float %b) {
+; CHECK-LABEL: fp_armv8_vminnm_o:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmov s0, r0
+; CHECK-NEXT: vmov s2, r1
+; CHECK-NEXT: vcmp.f32 s2, s0
+; CHECK-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-NEXT: vselgt.f32 s0, s0, s2
+; CHECK-NEXT: vmov r0, s0
+; CHECK-NEXT: bx lr
%cmp = fcmp olt float %a, %b
%cond = select nsz i1 %cmp, float %a, float %b
ret float %cond
}
-define double @fp-armv8_vminnm_ole(double %a, double %b) {
-; CHECK-LABEL: "fp-armv8_vminnm_ole":
-; CHECK-NOT: vminnm.f64
+define double @fp_armv8_vminnm_ole(double %a, double %b) {
+; CHECK-LABEL: fp_armv8_vminnm_ole:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmov d16, r0, r1
+; CHECK-NEXT: vmov d17, r2, r3
+; CHECK-NEXT: vcmp.f64 d17, d16
+; CHECK-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-NEXT: vselge.f64 d16, d16, d17
+; CHECK-NEXT: vmov r0, r1, d16
+; CHECK-NEXT: bx lr
%cmp = fcmp ole double %a, %b
%cond = select nsz i1 %cmp, double %a, double %b
ret double %cond
}
-define float @fp-armv8_vminnm_o_rev(float %a, float %b) {
-; CHECK-LABEL: "fp-armv8_vminnm_o_rev":
-; CHECK-NOT: vminnm.f32
+define float @fp_armv8_vminnm_o_rev(float %a, float %b) {
+; CHECK-LABEL: fp_armv8_vminnm_o_rev:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmov s0, r1
+; CHECK-NEXT: vmov s2, r0
+; CHECK-NEXT: vcmp.f32 s2, s0
+; CHECK-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-NEXT: vselgt.f32 s0, s0, s2
+; CHECK-NEXT: vmov r0, s0
+; CHECK-NEXT: bx lr
%cmp = fcmp ogt float %a, %b
%cond = select nsz i1 %cmp, float %b, float %a
ret float %cond
}
-define double @fp-armv8_vminnm_oge_rev(double %a, double %b) {
-; CHECK-LABEL: "fp-armv8_vminnm_oge_rev":
-; CHECK-NOT: vminnm.f64
+define double @fp_armv8_vminnm_oge_rev(double %a, double %b) {
+; CHECK-LABEL: fp_armv8_vminnm_oge_rev:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmov d16, r2, r3
+; CHECK-NEXT: vmov d17, r0, r1
+; CHECK-NEXT: vcmp.f64 d17, d16
+; CHECK-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-NEXT: vselge.f64 d16, d16, d17
+; CHECK-NEXT: vmov r0, r1, d16
+; CHECK-NEXT: bx lr
%cmp = fcmp oge double %a, %b
%cond = select nsz i1 %cmp, double %b, double %a
ret double %cond
}
-define float @fp-armv8_vminnm_u(float %a, float %b) {
-; CHECK-LABEL: "fp-armv8_vminnm_u":
-; CHECK-NOT: vminnm.f32
+define float @fp_armv8_vminnm_u(float %a, float %b) {
+; CHECK-LABEL: fp_armv8_vminnm_u:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmov s0, r1
+; CHECK-NEXT: vmov s2, r0
+; CHECK-NEXT: vcmp.f32 s2, s0
+; CHECK-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-NEXT: vselge.f32 s0, s0, s2
+; CHECK-NEXT: vmov r0, s0
+; CHECK-NEXT: bx lr
%cmp = fcmp ult float %a, %b
%cond = select nsz i1 %cmp, float %a, float %b
ret float %cond
}
-define float @fp-armv8_vminnm_ule(float %a, float %b) {
-; CHECK-LABEL: "fp-armv8_vminnm_ule":
-; CHECK-NOT: vminnm.f32
+define float @fp_armv8_vminnm_ule(float %a, float %b) {
+; CHECK-LABEL: fp_armv8_vminnm_ule:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmov s0, r1
+; CHECK-NEXT: vmov s2, r0
+; CHECK-NEXT: vcmp.f32 s2, s0
+; CHECK-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-NEXT: vselgt.f32 s0, s0, s2
+; CHECK-NEXT: vmov r0, s0
+; CHECK-NEXT: bx lr
%cmp = fcmp ule float %a, %b
%cond = select nsz i1 %cmp, float %a, float %b
ret float %cond
}
-define float @fp-armv8_vminnm_u_rev(float %a, float %b) {
-; CHECK-LABEL: "fp-armv8_vminnm_u_rev":
-; CHECK-NOT: vminnm.f32
+define float @fp_armv8_vminnm_u_rev(float %a, float %b) {
+; CHECK-LABEL: fp_armv8_vminnm_u_rev:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmov s0, r0
+; CHECK-NEXT: vmov s2, r1
+; CHECK-NEXT: vcmp.f32 s2, s0
+; CHECK-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-NEXT: vselge.f32 s0, s0, s2
+; CHECK-NEXT: vmov r0, s0
+; CHECK-NEXT: bx lr
%cmp = fcmp ugt float %a, %b
%cond = select nsz i1 %cmp, float %b, float %a
ret float %cond
}
-define double @fp-armv8_vminnm_uge_rev(double %a, double %b) {
-; CHECK-LABEL: "fp-armv8_vminnm_uge_rev":
-; CHECK-NOT: vminnm.f64
+define double @fp_armv8_vminnm_uge_rev(double %a, double %b) {
+; CHECK-LABEL: fp_armv8_vminnm_uge_rev:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmov d16, r0, r1
+; CHECK-NEXT: vmov d17, r2, r3
+; CHECK-NEXT: vcmp.f64 d17, d16
+; CHECK-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-NEXT: vselgt.f64 d16, d16, d17
+; CHECK-NEXT: vmov r0, r1, d16
+; CHECK-NEXT: bx lr
%cmp = fcmp uge double %a, %b
%cond = select nsz i1 %cmp, double %b, double %a
ret double %cond
}
-define float @fp-armv8_vmaxnm_o(float %a, float %b) {
-; CHECK-LABEL: "fp-armv8_vmaxnm_o":
-; CHECK-NOT: vmaxnm.f32
+define float @fp_armv8_vmaxnm_o(float %a, float %b) {
+; CHECK-LABEL: fp_armv8_vmaxnm_o:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmov s0, r1
+; CHECK-NEXT: vmov s2, r0
+; CHECK-NEXT: vcmp.f32 s2, s0
+; CHECK-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-NEXT: vselgt.f32 s0, s2, s0
+; CHECK-NEXT: vmov r0, s0
+; CHECK-NEXT: bx lr
%cmp = fcmp ogt float %a, %b
%cond = select nsz i1 %cmp, float %a, float %b
ret float %cond
}
-define float @fp-armv8_vmaxnm_oge(float %a, float %b) {
-; CHECK-LABEL: "fp-armv8_vmaxnm_oge":
-; CHECK-NOT: vmaxnm.f32
+define float @fp_armv8_vmaxnm_oge(float %a, float %b) {
+; CHECK-LABEL: fp_armv8_vmaxnm_oge:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmov s0, r1
+; CHECK-NEXT: vmov s2, r0
+; CHECK-NEXT: vcmp.f32 s2, s0
+; CHECK-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-NEXT: vselge.f32 s0, s2, s0
+; CHECK-NEXT: vmov r0, s0
+; CHECK-NEXT: bx lr
%cmp = fcmp oge float %a, %b
%cond = select nsz i1 %cmp, float %a, float %b
ret float %cond
}
-define float @fp-armv8_vmaxnm_o_rev(float %a, float %b) {
-; CHECK-LABEL: "fp-armv8_vmaxnm_o_rev":
-; CHECK-NOT: vmaxnm.f32
+define float @fp_armv8_vmaxnm_o_rev(float %a, float %b) {
+; CHECK-LABEL: fp_armv8_vmaxnm_o_rev:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmov s0, r0
+; CHECK-NEXT: vmov s2, r1
+; CHECK-NEXT: vcmp.f32 s2, s0
+; CHECK-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-NEXT: vselgt.f32 s0, s2, s0
+; CHECK-NEXT: vmov r0, s0
+; CHECK-NEXT: bx lr
%cmp = fcmp olt float %a, %b
%cond = select nsz i1 %cmp, float %b, float %a
ret float %cond
}
-define float @fp-armv8_vmaxnm_ole_rev(float %a, float %b) {
-; CHECK-LABEL: "fp-armv8_vmaxnm_ole_rev":
-; CHECK-NOT: vmaxnm.f32
+define float @fp_armv8_vmaxnm_ole_rev(float %a, float %b) {
+; CHECK-LABEL: fp_armv8_vmaxnm_ole_rev:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmov s0, r0
+; CHECK-NEXT: vmov s2, r1
+; CHECK-NEXT: vcmp.f32 s2, s0
+; CHECK-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-NEXT: vselge.f32 s0, s2, s0
+; CHECK-NEXT: vmov r0, s0
+; CHECK-NEXT: bx lr
%cmp = fcmp ole float %a, %b
%cond = select nsz i1 %cmp, float %b, float %a
ret float %cond
}
-define float @fp-armv8_vmaxnm_u(float %a, float %b) {
-; CHECK-LABEL: "fp-armv8_vmaxnm_u":
-; CHECK-NOT: vmaxnm.f32
+define float @fp_armv8_vmaxnm_u(float %a, float %b) {
+; CHECK-LABEL: fp_armv8_vmaxnm_u:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmov s0, r0
+; CHECK-NEXT: vmov s2, r1
+; CHECK-NEXT: vcmp.f32 s2, s0
+; CHECK-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-NEXT: vselge.f32 s0, s2, s0
+; CHECK-NEXT: vmov r0, s0
+; CHECK-NEXT: bx lr
%cmp = fcmp ugt float %a, %b
%cond = select nsz i1 %cmp, float %a, float %b
ret float %cond
}
-define float @fp-armv8_vmaxnm_uge(float %a, float %b) {
-; CHECK-LABEL: "fp-armv8_vmaxnm_uge":
-; CHECK-NOT: vmaxnm.f32
+define float @fp_armv8_vmaxnm_uge(float %a, float %b) {
+; CHECK-LABEL: fp_armv8_vmaxnm_uge:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmov s0, r0
+; CHECK-NEXT: vmov s2, r1
+; CHECK-NEXT: vcmp.f32 s2, s0
+; CHECK-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-NEXT: vselgt.f32 s0, s2, s0
+; CHECK-NEXT: vmov r0, s0
+; CHECK-NEXT: bx lr
%cmp = fcmp uge float %a, %b
%cond = select nsz i1 %cmp, float %a, float %b
ret float %cond
}
-define float @fp-armv8_vmaxnm_u_rev(float %a, float %b) {
-; CHECK-LABEL: "fp-armv8_vmaxnm_u_rev":
-; CHECK-NOT: vmaxnm.f32
+define float @fp_armv8_vmaxnm_u_rev(float %a, float %b) {
+; CHECK-LABEL: fp_armv8_vmaxnm_u_rev:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmov s0, r1
+; CHECK-NEXT: vmov s2, r0
+; CHECK-NEXT: vcmp.f32 s2, s0
+; CHECK-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-NEXT: vselge.f32 s0, s2, s0
+; CHECK-NEXT: vmov r0, s0
+; CHECK-NEXT: bx lr
%cmp = fcmp ult float %a, %b
%cond = select nsz i1 %cmp, float %b, float %a
ret float %cond
}
-define double @fp-armv8_vmaxnm_ule_rev(double %a, double %b) {
-; CHECK-LABEL: "fp-armv8_vmaxnm_ule_rev":
-; CHECK-NOT: vmaxnm.f64
+define double @fp_armv8_vmaxnm_ule_rev(double %a, double %b) {
+; CHECK-LABEL: fp_armv8_vmaxnm_ule_rev:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmov d16, r2, r3
+; CHECK-NEXT: vmov d17, r0, r1
+; CHECK-NEXT: vcmp.f64 d17, d16
+; CHECK-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-NEXT: vselgt.f64 d16, d17, d16
+; CHECK-NEXT: vmov r0, r1, d16
+; CHECK-NEXT: bx lr
%cmp = fcmp ule double %a, %b
%cond = select nsz i1 %cmp, double %b, double %a
ret double %cond
@@ -170,10 +305,22 @@ define double @fp-armv8_vmaxnm_ule_rev(double %a, double %b) {
; known non-NaNs
-define float @fp-armv8_vminnm_NNNo(float %a) {
-; CHECK-LABEL: "fp-armv8_vminnm_NNNo":
-; CHECK: vminnm.f32
-; CHECK-NOT: vminnm.f32
+define float @fp_armv8_vminnm_NNNo(float %a) {
+; CHECK-LABEL: fp_armv8_vminnm_NNNo:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmov.f32 s0, #1.200000e+01
+; CHECK-NEXT: vldr s2, .LCPI20_0
+; CHECK-NEXT: vmov s4, r0
+; CHECK-NEXT: vminnm.f32 s0, s4, s0
+; CHECK-NEXT: vcmp.f32 s0, s2
+; CHECK-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-NEXT: vselgt.f32 s0, s2, s0
+; CHECK-NEXT: vmov r0, s0
+; CHECK-NEXT: bx lr
+; CHECK-NEXT: .p2align 2
+; CHECK-NEXT: @ %bb.1:
+; CHECK-NEXT: .LCPI20_0:
+; CHECK-NEXT: .long 0x42080000 @ float 34
%cmp1 = fcmp olt float %a, 12.
%cond1 = select nsz i1 %cmp1, float %a, float 12.
%cmp2 = fcmp olt float 34., %cond1
@@ -181,10 +328,26 @@ define float @fp-armv8_vminnm_NNNo(float %a) {
ret float %cond2
}
-define double @fp-armv8_vminnm_NNNole(double %a) {
-; CHECK-LABEL: "fp-armv8_vminnm_NNNole":
-; CHECK: vminnm.f64
-; CHECK-NOT: vminnm.f64
+define double @fp_armv8_vminnm_NNNole(double %a) {
+; CHECK-LABEL: fp_armv8_vminnm_NNNole:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vldr d16, .LCPI21_0
+; CHECK-NEXT: vmov d18, r0, r1
+; CHECK-NEXT: vldr d17, .LCPI21_1
+; CHECK-NEXT: vminnm.f64 d16, d18, d16
+; CHECK-NEXT: vcmp.f64 d16, d17
+; CHECK-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-NEXT: vselge.f64 d16, d17, d16
+; CHECK-NEXT: vmov r0, r1, d16
+; CHECK-NEXT: bx lr
+; CHECK-NEXT: .p2align 3
+; CHECK-NEXT: @ %bb.1:
+; CHECK-NEXT: .LCPI21_0:
+; CHECK-NEXT: .long 0 @ double 34
+; CHECK-NEXT: .long 1078001664
+; CHECK-NEXT: .LCPI21_1:
+; CHECK-NEXT: .long 0 @ double 56
+; CHECK-NEXT: .long 1078722560
%cmp1 = fcmp ole double %a, 34.
%cond1 = select nsz i1 %cmp1, double %a, double 34.
%cmp2 = fcmp ole double 56., %cond1
@@ -192,10 +355,24 @@ define double @fp-armv8_vminnm_NNNole(double %a) {
ret double %cond2
}
-define float @fp-armv8_vminnm_NNNo_rev(float %a) {
-; CHECK-LABEL: "fp-armv8_vminnm_NNNo_rev":
-; CHECK: vminnm.f32
-; CHECK-NOT: vminnm.f32
+define float @fp_armv8_vminnm_NNNo_rev(float %a) {
+; CHECK-LABEL: fp_armv8_vminnm_NNNo_rev:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vldr s0, .LCPI22_0
+; CHECK-NEXT: vmov s2, r0
+; CHECK-NEXT: vldr s4, .LCPI22_1
+; CHECK-NEXT: vcmp.f32 s2, s0
+; CHECK-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-NEXT: vselgt.f32 s0, s0, s2
+; CHECK-NEXT: vminnm.f32 s0, s0, s4
+; CHECK-NEXT: vmov r0, s0
+; CHECK-NEXT: bx lr
+; CHECK-NEXT: .p2align 2
+; CHECK-NEXT: @ %bb.1:
+; CHECK-NEXT: .LCPI22_0:
+; CHECK-NEXT: .long 0x42600000 @ float 56
+; CHECK-NEXT: .LCPI22_1:
+; CHECK-NEXT: .long 0x429c0000 @ float 78
%cmp1 = fcmp ogt float %a, 56.
%cond1 = select nsz i1 %cmp1, float 56., float %a
%cmp2 = fcmp ogt float 78., %cond1
@@ -203,10 +380,26 @@ define float @fp-armv8_vminnm_NNNo_rev(float %a) {
ret float %cond2
}
-define double @fp-armv8_vminnm_NNNoge_rev(double %a) {
-; CHECK-LABEL: "fp-armv8_vminnm_NNNoge_rev":
-; CHECK: vminnm.f64
-; CHECK-NOT: vminnm.f64
+define double @fp_armv8_vminnm_NNNoge_rev(double %a) {
+; CHECK-LABEL: fp_armv8_vminnm_NNNoge_rev:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vldr d16, .LCPI23_0
+; CHECK-NEXT: vmov d17, r0, r1
+; CHECK-NEXT: vldr d18, .LCPI23_1
+; CHECK-NEXT: vcmp.f64 d17, d16
+; CHECK-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-NEXT: vselge.f64 d16, d16, d17
+; CHECK-NEXT: vminnm.f64 d16, d16, d18
+; CHECK-NEXT: vmov r0, r1, d16
+; CHECK-NEXT: bx lr
+; CHECK-NEXT: .p2align 3
+; CHECK-NEXT: @ %bb.1:
+; CHECK-NEXT: .LCPI23_0:
+; CHECK-NEXT: .long 0 @ double 78
+; CHECK-NEXT: .long 1079214080
+; CHECK-NEXT: .LCPI23_1:
+; CHECK-NEXT: .long 0 @ double 90
+; CHECK-NEXT: .long 1079410688
%cmp1 = fcmp oge double %a, 78.
%cond1 = select nsz i1 %cmp1, double 78., double %a
%cmp2 = fcmp oge double 90., %cond1
@@ -214,10 +407,22 @@ define double @fp-armv8_vminnm_NNNoge_rev(double %a) {
ret double %cond2
}
-define float @fp-armv8_vminnm_NNNu(float %b) {
-; CHECK-LABEL: "fp-armv8_vminnm_NNNu":
-; CHECK: vminnm.f32
-; CHECK-NOT: vminnm.f32
+define float @fp_armv8_vminnm_NNNu(float %b) {
+; CHECK-LABEL: fp_armv8_vminnm_NNNu:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmov.f32 s0, #1.200000e+01
+; CHECK-NEXT: vldr s2, .LCPI24_0
+; CHECK-NEXT: vmov s4, r0
+; CHECK-NEXT: vminnm.f32 s0, s4, s0
+; CHECK-NEXT: vcmp.f32 s2, s0
+; CHECK-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-NEXT: vselgt.f32 s0, s0, s2
+; CHECK-NEXT: vmov r0, s0
+; CHECK-NEXT: bx lr
+; CHECK-NEXT: .p2align 2
+; CHECK-NEXT: @ %bb.1:
+; CHECK-NEXT: .LCPI24_0:
+; CHECK-NEXT: .long 0x42080000 @ float 34
%cmp1 = fcmp ult float 12., %b
%cond1 = select nsz i1 %cmp1, float 12., float %b
%cmp2 = fcmp ult float %cond1, 34.
@@ -225,10 +430,24 @@ define float @fp-armv8_vminnm_NNNu(float %b) {
ret float %cond2
}
-define float @fp-armv8_vminnm_NNNule(float %b) {
-; CHECK-LABEL: "fp-armv8_vminnm_NNNule":
-; CHECK: vminnm.f32
-; CHECK-NOT: vminnm.f32
+define float @fp_armv8_vminnm_NNNule(float %b) {
+; CHECK-LABEL: fp_armv8_vminnm_NNNule:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vldr s0, .LCPI25_0
+; CHECK-NEXT: vmov s4, r0
+; CHECK-NEXT: vldr s2, .LCPI25_1
+; CHECK-NEXT: vminnm.f32 s0, s4, s0
+; CHECK-NEXT: vcmp.f32 s2, s0
+; CHECK-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-NEXT: vselge.f32 s0, s0, s2
+; CHECK-NEXT: vmov r0, s0
+; CHECK-NEXT: bx lr
+; CHECK-NEXT: .p2align 2
+; CHECK-NEXT: @ %bb.1:
+; CHECK-NEXT: .LCPI25_0:
+; CHECK-NEXT: .long 0x42080000 @ float 34
+; CHECK-NEXT: .LCPI25_1:
+; CHECK-NEXT: .long 0x42600000 @ float 56
%cmp1 = fcmp ule float 34., %b
%cond1 = select nsz i1 %cmp1, float 34., float %b
%cmp2 = fcmp ule float %cond1, 56.
@@ -236,10 +455,24 @@ define float @fp-armv8_vminnm_NNNule(float %b) {
ret float %cond2
}
-define float @fp-armv8_vminnm_NNNu_rev(float %b) {
-; CHECK-LABEL: "fp-armv8_vminnm_NNNu_rev":
-; CHECK: vminnm.f32
-; CHECK-NOT: vminnm.f32
+define float @fp_armv8_vminnm_NNNu_rev(float %b) {
+; CHECK-LABEL: fp_armv8_vminnm_NNNu_rev:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vldr s0, .LCPI26_0
+; CHECK-NEXT: vmov s2, r0
+; CHECK-NEXT: vldr s4, .LCPI26_1
+; CHECK-NEXT: vcmp.f32 s2, s0
+; CHECK-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-NEXT: vselge.f32 s0, s0, s2
+; CHECK-NEXT: vminnm.f32 s0, s0, s4
+; CHECK-NEXT: vmov r0, s0
+; CHECK-NEXT: bx lr
+; CHECK-NEXT: .p2align 2
+; CHECK-NEXT: @ %bb.1:
+; CHECK-NEXT: .LCPI26_0:
+; CHECK-NEXT: .long 0x42600000 @ float 56
+; CHECK-NEXT: .LCPI26_1:
+; CHECK-NEXT: .long 0x429c0000 @ float 78
%cmp1 = fcmp ugt float 56., %b
%cond1 = select nsz i1 %cmp1, float %b, float 56.
%cmp2 = fcmp ugt float %cond1, 78.
@@ -247,10 +480,26 @@ define float @fp-armv8_vminnm_NNNu_rev(float %b) {
ret float %cond2
}
-define double @fp-armv8_vminnm_NNNuge_rev(double %b) {
-; CHECK-LABEL: "fp-armv8_vminnm_NNNuge_rev":
-; CHECK: vminnm.f64
-; CHECK-NOT: vminnm.f64
+define double @fp_armv8_vminnm_NNNuge_rev(double %b) {
+; CHECK-LABEL: fp_armv8_vminnm_NNNuge_rev:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vldr d16, .LCPI27_0
+; CHECK-NEXT: vmov d17, r0, r1
+; CHECK-NEXT: vldr d18, .LCPI27_1
+; CHECK-NEXT: vcmp.f64 d17, d16
+; CHECK-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-NEXT: vselgt.f64 d16, d16, d17
+; CHECK-NEXT: vminnm.f64 d16, d16, d18
+; CHECK-NEXT: vmov r0, r1, d16
+; CHECK-NEXT: bx lr
+; CHECK-NEXT: .p2align 3
+; CHECK-NEXT: @ %bb.1:
+; CHECK-NEXT: .LCPI27_0:
+; CHECK-NEXT: .long 0 @ double 78
+; CHECK-NEXT: .long 1079214080
+; CHECK-NEXT: .LCPI27_1:
+; CHECK-NEXT: .long 0 @ double 90
+; CHECK-NEXT: .long 1079410688
%cmp1 = fcmp uge double 78., %b
%cond1 = select nsz i1 %cmp1, double %b, double 78.
%cmp2 = fcmp uge double %cond1, 90.
@@ -258,10 +507,22 @@ define double @fp-armv8_vminnm_NNNuge_rev(double %b) {
ret double %cond2
}
-define float @fp-armv8_vmaxnm_NNNo(float %a) {
-; CHECK-LABEL: "fp-armv8_vmaxnm_NNNo":
-; CHECK: vmaxnm...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/184574
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