[llvm] SelectionDAG: Support FMINIMUMNUM and FMINIMUM in combineMinNumMaxNumImpl (PR #137449)

[YunQiang Su via llvm-commits]

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@@ -0,0 +1,91 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc --mtriple=aarch64 --mattr=+fullfp16 < %s | FileCheck  %s --check-prefixes=CHECK,FP16
+; RUN: llc --mtriple=aarch64 --mattr=-fullfp16 < %s | FileCheck  %s --check-prefixes=CHECK,NOFP16
+
+define float @maxf(float %a, float %b) {
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wzssyqa wrote:

Yes. As ARM64 has FMAXNUM_IEEE Legal. I added it for be sure that it works well on such backend.

https://github.com/llvm/llvm-project/pull/137449