[llvm] SelectionDAG: Support FMINIMUMNUM and FMINIMUM in combineMinNumMaxNumImpl (PR #137449)

[YunQiang Su via llvm-commits]

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@@ -12226,38 +12253,41 @@ static SDValue combineMinNumMaxNumImpl(const SDLoc &DL, EVT VT, SDValue LHS,
                                        const TargetLowering &TLI,
                                        SelectionDAG &DAG) {
   EVT TransformVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
+  unsigned Opcode = ISD::DELETED_NODE;
+  bool Max = true;
   switch (CC) {
   case ISD::SETOLT:
   case ISD::SETOLE:
   case ISD::SETLT:
   case ISD::SETLE:
   case ISD::SETULT:
   case ISD::SETULE: {
-    // Since it's known never nan to get here already, either fminnum or
-    // fminnum_ieee are OK. Try the ieee version first, since it's fminnum is
-    // expanded in terms of it.
-    unsigned IEEEOpcode = (LHS == True) ? ISD::FMINNUM_IEEE : ISD::FMAXNUM_IEEE;
-    if (TLI.isOperationLegalOrCustom(IEEEOpcode, VT))
-      return DAG.getNode(IEEEOpcode, DL, VT, LHS, RHS);
-
-    unsigned Opcode = (LHS == True) ? ISD::FMINNUM : ISD::FMAXNUM;
-    if (TLI.isOperationLegalOrCustom(Opcode, TransformVT))
-      return DAG.getNode(Opcode, DL, VT, LHS, RHS);
-    return SDValue();
+    Max = LHS != True;
+    Opcode = Max ? ISD::FMAXNUM : ISD::FMINNUM;
   }
+    [[fallthrough]];
   case ISD::SETOGT:
   case ISD::SETOGE:
   case ISD::SETGT:
   case ISD::SETGE:
   case ISD::SETUGT:
   case ISD::SETUGE: {
-    unsigned IEEEOpcode = (LHS == True) ? ISD::FMAXNUM_IEEE : ISD::FMINNUM_IEEE;
-    if (TLI.isOperationLegalOrCustom(IEEEOpcode, VT))
-      return DAG.getNode(IEEEOpcode, DL, VT, LHS, RHS);
-
-    unsigned Opcode = (LHS == True) ? ISD::FMAXNUM : ISD::FMINNUM;
+    if (Opcode == ISD::DELETED_NODE) {
+      // Since it's known never nan to get here already, either fminimumnum,
+      // fminimum, fminnum, or fminnum_ieee are OK. Try Legal first and then
+      // Custom.
+      Max = LHS == True;
+      Opcode = Max ? ISD::FMAXNUM : ISD::FMINNUM;
+    }
+    unsigned MinMaxOpc = getBestMinMaxOpc(TLI, VT, Max);
+    SDNodeFlags Flags;
+    Flags.setNoNaNs(true);
+    Flags.setNoSignedZeros(true);
----------------
wzssyqa wrote:

1. For nnan, this function is only called if fcmp+select with assert nnan.
2. for nsz, fcmp+select doesn't process singed zeroes at all.

Add nnan and nsz can ask the backend to generate optimize code if `isOperationCustom`

https://github.com/llvm/llvm-project/pull/137449