[llvm] [X86][APX] Add a few pseudo opcodes support EGPR (PR #184550)

[Phoebe Wang via llvm-commits]

https://github.com/phoebewang created https://github.com/llvm/llvm-project/pull/184550

Found in post testing in #180242

>From a2e01da13c0684149a449d820bd4dbe7ec78fb1c Mon Sep 17 00:00:00 2001
From: Phoebe Wang <phoebe.wang at intel.com>
Date: Wed, 4 Mar 2026 14:00:32 +0800
Subject: [PATCH] [X86][APX] Add a few pseudo opcodes support EGPR

Found in post testing in #180242
---
 .../lib/Target/X86/MCTargetDesc/X86BaseInfo.h | 37 +++++++++++++++----
 llvm/test/CodeGen/X86/reserveRreg.ll          |  2 +-
 2 files changed, 30 insertions(+), 9 deletions(-)

diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h b/llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h
index 569484704a249..06b13c0982d21 100644
--- a/llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h
+++ b/llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h
@@ -1265,14 +1265,35 @@ inline bool canUseApxExtendedReg(const MCInstrDesc &Desc) {
     return true;
 
   unsigned Opcode = Desc.Opcode;
-  // MOV32r0 is always expanded to XOR32rr
-  if (Opcode == X86::MOV32r0)
-    return true;
-  // To be conservative, egpr is not used for all pseudo instructions
-  // because we are not sure what instruction it will become.
-  // FIXME: Could we improve it in X86ExpandPseudo?
-  if (isPseudo(TSFlags))
-    return false;
+  if (isPseudo(TSFlags)) {
+    switch (Opcode) {
+    default:
+      // To be conservative, egpr is not used for all pseudo instructions
+      // because we are not sure what instruction it will become.
+      // FIXME: Could we improve it in X86ExpandPseudo?
+      return false;
+    case X86::MOV32r0:
+    case X86::MOV32r1:
+    case X86::MOV32r_1:
+      // They are always expanded to XOR32rr.
+      return true;
+    case X86::MOV32ri64:
+      // MOV32ri64 is always expanded to MOV32ri.
+      return true;
+    case X86::ADD8rr_DB:
+    case X86::ADD16rr_DB:
+    case X86::ADD32rr_DB:
+    case X86::ADD64rr_DB:
+      // They are always expanded to ORNrr.
+      return true;
+    case X86::ADD8ri_DB:
+    case X86::ADD16ri_DB:
+    case X86::ADD32ri_DB:
+    case X86::ADD64ri32_DB:
+      // They are always expanded to ORNri.
+      return true;
+    }
+  }
 
   // MAP OB/TB in legacy encoding space can always use egpr except
   // XSAVE*/XRSTOR*.
diff --git a/llvm/test/CodeGen/X86/reserveRreg.ll b/llvm/test/CodeGen/X86/reserveRreg.ll
index b6b10ad5169a4..1a28f10b05681 100644
--- a/llvm/test/CodeGen/X86/reserveRreg.ll
+++ b/llvm/test/CodeGen/X86/reserveRreg.ll
@@ -1,7 +1,7 @@
 ;; Check if manually reserved registers are always excluded from being saved by
 ;; the function prolog/epilog, even for callee-saved ones, as per GCC behavior.
 
-; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -verify-machineinstrs | FileCheck %s
 
 define preserve_mostcc void @t8() "target-features"="+reserve-r8" {
 ; CHECK-LABEL: t8: