[llvm] [RISCV] Lower i8/i16/i32 scalable vector ISD::CLMUL/CLMULH with Zvbc32e. (PR #184465)

[Pengcheng Wang via llvm-commits]

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@@ -1117,17 +1117,20 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
         }
       }
 
-      if (Subtarget.hasStdExtZvbc() && Subtarget.hasVInstructionsI64()) {
-        // TODO: Support Zvbc32e.
-        if (VT.getVectorElementType() == MVT::i64)
+      if (VT.getVectorElementType() == MVT::i64) {
+        if (Subtarget.hasStdExtZvbc())
           setOperationAction({ISD::CLMUL, ISD::CLMULH}, VT, Legal);
-        else {
+      } else {
+        if (Subtarget.hasStdExtZvbc32e()) {
+          setOperationAction({ISD::CLMUL, ISD::CLMULH}, VT, Legal);
+        } else if (Subtarget.hasStdExtZvbc() && Subtarget.hasVInstructionsI64()) {
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wangpc-pp wrote:

Does `Zvbc` imply `hasVInstructionsI64`?

https://github.com/llvm/llvm-project/pull/184465