[llvm] [RISCV] Lower i8/i16/i32 scalable vector ISD::CLMUL/CLMULH with Zvbc32e. (PR #184465)

Pengcheng Wang via llvm-commits llvm-commits at lists.llvm.org
Tue Mar 3 19:28:39 PST 2026

Previous message: [llvm] [RISCV] Remove OperandType OPERAND_SIMM10_UNSIGNED. Rename OPERAND_SIMM8_UNSIGNED->OPERAND_SIMM8 (PR #184540)
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https://github.com/wangpc-pp edited https://github.com/llvm/llvm-project/pull/184465

Previous message: [llvm] [RISCV] Remove OperandType OPERAND_SIMM10_UNSIGNED. Rename OPERAND_SIMM8_UNSIGNED->OPERAND_SIMM8 (PR #184540)
Next message: [llvm] [RISCV] Lower i8/i16/i32 scalable vector ISD::CLMUL/CLMULH with Zvbc32e. (PR #184465)
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