[llvm] b4dfa43 - [RISCV] Fix type inference ambiguity in SwapSysReg pattern (#184305)

[via llvm-commits]

Author: lihengda861-source
Date: 2026-03-03T11:57:38-08:00
New Revision: b4dfa43cb8aea45487033d1f21c49672ac33e02a

URL: https://github.com/llvm/llvm-project/commit/b4dfa43cb8aea45487033d1f21c49672ac33e02a
DIFF: https://github.com/llvm/llvm-project/commit/b4dfa43cb8aea45487033d1f21c49672ac33e02a.diff

LOG: [RISCV] Fix type inference ambiguity in SwapSysReg pattern (#184305)

Issue:
Building RISCVInstrInfo.td fails with the following TableGen error
during the generation of RISCVGenInstrInfo.inc:
     ` error: In test: Could not infer all types in pattern!`

Root Cause:
The riscv_swap_csr node has a polymorphic result type (i32 or i64
depending on the target architecture). When used inside the SwapSysReg
class pattern, TableGen's type inference engine cannot automatically
deduce the exact return type solely from the GPR:$rd output, leading to
the ambiguity error.

Fix:
This patch resolves the type ambiguity by explicitly wrapping the
riscv_swap_csr node with XLenVT, allowing TableGen to infer the types
correctly.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfo.td

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index a5c0e016aaa83..eb276ef17da75 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -2057,7 +2057,7 @@ class WriteSysRegImm<SysReg SR, list<Register> Regs>
 
 class SwapSysReg<SysReg SR, list<Register> Regs>
   : Pseudo<(outs GPR:$rd), (ins GPR:$val),
-           [(set GPR:$rd, (riscv_swap_csr (XLenVT SR.Encoding), (XLenVT GPR:$val)))]>,
+           [(set GPR:$rd, (XLenVT (riscv_swap_csr (XLenVT SR.Encoding), (XLenVT GPR:$val))))]>,
     PseudoInstExpansion<(CSRRW GPR:$rd, SR.Encoding, GPR:$val)> {
   let hasSideEffects = 0;
   let Uses = Regs;