[llvm] [WebAssembly] Fold extended vector shifts by constant to extmul (PR #184007)

[via llvm-commits]

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@@ -195,3 +195,47 @@ define <8 x i32> @zext_sext_mul_v8i16(<8 x i16> %a, <8 x i16> %b) {
   %mul = mul <8 x i32> %wide.a, %wide.b
   ret <8 x i32> %mul
 }
+
+define <4 x i32> @sext_mul_v8i16_with_symmetric_constant_vector(<8 x i16> %v) {
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ParkHanbum wrote:

As you suggested, I tried to process this before the vector is split (during DAGCombine). 
```
SelectionDAG has 27 nodes:
      t2: v8i16 = WebAssemblyISD::ARGUMENT TargetConstant:i32<0>
    t3: v8i32 = sign_extend t2
    t31: v8i32 = BUILD_VECTOR Constant:i32<12>, Constant:i32<0>, Constant:i32<12>, Constant:i32<0>, Constant:i32<12>, Constant:i32<0>, Constant:i32<12>, Constant:i32<0>
  t32: v8i32 = shl t3, t31
 ```
However, as you can see, both the LHS and RHS come in as v8i32 (256-bit vectors). It seems we cannot directly emit WebAssembly-specific nodes in this illegal state before type legalization splits them, correct?

It seems the only viable approach at this stage is to convert the shl back to a generic mul and mark the constant build_vector as opaque. This prevents the generic DAG combiner from folding it back into an shl, allowing it to eventually be lowered into an extmul after type legalization.

https://github.com/llvm/llvm-project/pull/184007