[llvm] [AMDGPU] Remove alignment constraint from spill pseudos (PR #177317)

[Matt Arsenault via llvm-commits]

================
@@ -1536,12 +1536,35 @@ void SIRegisterInfo::buildSpillLoadStore(
   const bool IsAGPR = !ST.hasGFX90AInsts() && isAGPRClass(RC);
   const unsigned RegWidth = AMDGPU::getRegBitWidth(*RC) / 8;
 
+  // On targets with register tuple alignment requirements,
+  // for unaligned tuples, break the spill into 32-bit pieces.
+  // TODO: Optimize misaligned spills by using larger aligned chunks instead of
+  // 32-bit splits.
+  bool IsRegMisaligned = false;
+  if (!IsBlock && RegWidth > 4) {
+    unsigned SpillOpcode =
+        getFlatScratchSpillOpcode(TII, LoadStoreOp, std::min(RegWidth, 16u));
+    int VDataIdx =
+        IsStore ? AMDGPU::getNamedOperandIdx(SpillOpcode, AMDGPU::OpName::vdata)
+                : 0; // Restore Ops have data reg as the first (output) operand.
+    const TargetRegisterClass *ExpectedRC =
+        TII->getRegClass(TII->get(SpillOpcode), VDataIdx);
+    unsigned NumRegs = std::min(RegWidth / 4, 4u);
+    unsigned SubIdx = getSubRegFromChannel(0, NumRegs);
+    const TargetRegisterClass *MatchRC = findCommonRegClass(
+        RC, getRegSizeInBits(*ExpectedRC) == getRegSizeInBits(*RC) ? 0 : SubIdx,
+        ExpectedRC, 0);
+    if (MatchRC && !MatchRC->contains(ValueReg))
+      IsRegMisaligned = true;
+  }
----------------
arsenm wrote:

```suggestion
    const TargetRegisterClass *ExpectedRC =
        TII->getRegClass(TII->get(SpillOpcode), VDataIdx);

    if (!ExpectedRC->contains(ValueReg)) {
      unsigned NumRegs = std::min(AMDGPU::getRegBitWidth(*ExpectedRC) / 4, 4u);
      unsigned SubIdx = getSubRegFromChannel(0, NumRegs);

      const TargetRegisterClass *MatchRC =
          getMatchingSuperRegClass(RC, ExpectedRC, SubIdx);
      if (!MatchRC || !MatchRC->contains(ValueReg))
        IsRegMisaligned = true;
    }
  }
```

https://github.com/llvm/llvm-project/pull/177317