[llvm] [TableGen] Complete the support for artificial registers (PR #183371)

[Matt Arsenault via llvm-commits]

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@@ -502,12 +502,16 @@ class CodeGenRegisterClass {
   struct Key {
     const CodeGenRegister::Vec *Members;
     RegSizeInfoByHwMode RSI;
+    bool IgnoreArtificialMembers;
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arsenm wrote:

Document this field. I'm not really sure why you would ever want to make it false 

https://github.com/llvm/llvm-project/pull/183371