[llvm] [RISCV] Promote i8/i16/i32 scalable vector CLMUL to i64 CLMUL with Zvbc. (PR #184265)

[Ramkumar Ramachandra via llvm-commits]

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@@ -8921,6 +8932,18 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
       return lowerToScalableOp(Op, DAG);
     assert(Op.getOpcode() != ISD::CTTZ);
     return lowerCTLZ_CTTZ_ZERO_UNDEF(Op, DAG);
+  case ISD::CLMUL: {
+    assert(Op.getValueType().isScalableVector() && Subtarget.hasStdExtZvbc() &&
+           "Unexpected custom legalisation");
+    // Promote to i64 vector.
+    MVT VT = Op.getSimpleValueType();
+    MVT I64VecVT = MVT::getVectorVT(MVT::i64, VT.getVectorElementCount());
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artagnon wrote:

```suggestion
    MVT I64VecVT = VT.changeElementType(MVT::i64);
```

https://github.com/llvm/llvm-project/pull/184265