[llvm] [AArch64] Prefer `SADDLV` over `ADDV` for vector mask reductions (PR #183522)

[Paul Walker via llvm-commits]

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@@ -989,6 +989,18 @@ bool AArch64DAGToDAGISel::SelectArithExtendedRegister(SDValue N, SDValue &Reg,
     if (Ext == AArch64_AM::InvalidShiftExtend)
       return false;
 
+    // Don't match sext of vector extracts. These can use SMOV, but if we match
+    // this an extended register, we'll always fold the extend into an ALU op
+    // user of the extend (which results in a UMOV).
+    if (Ext >= AArch64_AM::SXTB) {
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paulwalker-arm wrote:

We should not rely on these being at the end of the enum. Perhaps move `isSignExtendShiftType` into AArch64AddressingModes.h?

https://github.com/llvm/llvm-project/pull/183522