[llvm] [AArch64] Limit support to f32 and f64 in performSelectCombine (PR #184315)

[David Green via llvm-commits]

https://github.com/davemgreen created https://github.com/llvm/llvm-project/pull/184315

This prevents a crash with fp128 types, other types (f16) were already excluded.

>From c9d8322ff7054620e2b7f6125532d82fb1f8d94e Mon Sep 17 00:00:00 2001
From: David Green <david.green at arm.com>
Date: Tue, 3 Mar 2026 10:25:27 +0000
Subject: [PATCH] [AArch64] Limit support to f32 and f64 in
 performSelectCombine

This prevents a crash with fp128 types, other types (f16) were already
excluded.
---
 .../Target/AArch64/AArch64ISelLowering.cpp    |  2 +-
 .../CodeGen/AArch64/arm64-neon-select_cc.ll   | 36 +++++++++++++++++++
 2 files changed, 37 insertions(+), 1 deletion(-)

diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 3f0915e9d0fcb..571b29682f065 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -27977,7 +27977,7 @@ static SDValue performSelectCombine(SDNode *N,
   // ruled out to prevent the creation of setcc that need to be scalarized.
   EVT SrcVT = N0.getOperand(0).getValueType();
   if (SrcVT == MVT::i1 ||
-      (SrcVT.isFloatingPoint() && SrcVT.getSizeInBits() <= 16))
+      (SrcVT.isFloatingPoint() && SrcVT != MVT::f32 && SrcVT != MVT::f64))
     return SDValue();
 
   // If NumMaskElts == 0, the comparison is larger than select result. The
diff --git a/llvm/test/CodeGen/AArch64/arm64-neon-select_cc.ll b/llvm/test/CodeGen/AArch64/arm64-neon-select_cc.ll
index cad3fb58086d6..76583367c9d9b 100644
--- a/llvm/test/CodeGen/AArch64/arm64-neon-select_cc.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-neon-select_cc.ll
@@ -304,4 +304,40 @@ define <3 x float> @test_select_cc_v3f32_fcmp_f64(<3 x float> %a, <3 x float> %b
   ret <3 x float> %r
 }
 
+define <2 x double> @test_select_cc_v2f64_fp128(fp128 %a, fp128 %b, <2 x double> %c, <2 x double> %d) {
+; CHECK-LABEL: test_select_cc_v2f64_fp128:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    sub sp, sp, #48
+; CHECK-NEXT:    str x30, [sp, #32] // 8-byte Spill
+; CHECK-NEXT:    .cfi_def_cfa_offset 48
+; CHECK-NEXT:    .cfi_offset w30, -16
+; CHECK-NEXT:    stp q2, q3, [sp] // 32-byte Folded Spill
+; CHECK-NEXT:    bl __eqtf2
+; CHECK-NEXT:    cmp w0, #0
+; CHECK-NEXT:    ldp q2, q1, [sp] // 32-byte Folded Reload
+; CHECK-NEXT:    csetm x8, eq
+; CHECK-NEXT:    ldr x30, [sp, #32] // 8-byte Reload
+; CHECK-NEXT:    dup v0.2d, x8
+; CHECK-NEXT:    bsl v0.16b, v2.16b, v1.16b
+; CHECK-NEXT:    add sp, sp, #48
+; CHECK-NEXT:    ret
+  %cmp31 = fcmp oeq fp128 %a, %b
+  %e = select i1 %cmp31, <2 x double> %c, <2 x double> %d
+  ret <2 x double> %e
+}
+
+define <2 x double> @test_select_cc_v2f64_i128(i128 %a, i128 %b, <2 x double> %c, <2 x double> %d) {
+; CHECK-LABEL: test_select_cc_v2f64_i128:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    cmp x0, x2
+; CHECK-NEXT:    sbcs xzr, x1, x3
+; CHECK-NEXT:    csetm x8, lo
+; CHECK-NEXT:    dup v2.2d, x8
+; CHECK-NEXT:    bif v0.16b, v1.16b, v2.16b
+; CHECK-NEXT:    ret
+  %cmp31 = icmp ult i128 %a, %b
+  %e = select i1 %cmp31, <2 x double> %c, <2 x double> %d
+  ret <2 x double> %e
+}
+
 attributes #0 = { nounwind}